Imaging systems having dual storage gate overflow capabilities

• US 10,560,649 B2
• Filed: 02/20/2018
• Issued: 02/11/2020
• Est. Priority Date: 02/20/2018
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Geurts, Tomas
• Primary Examiner(s): Hannett, James M
• Application Number:
  US15/900,136
• Publication Number:
  US 20190260949A1
• Time in Patent Office: 721 Days
• Field of Search: None
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/589 with different integration times, e.g. short and long exposures
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/617 for reducing electromagnetic interference, e.g. clocking noise
• CPC Class Codes: H04N 25/626 Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An image sensor pixel may include a photodiode that generates first charge for a first frame and second charge for a second frame, first and second storage gates coupled to the photodiode, a floating diffusion coupled to the first storage gate through a first transistor, a second transistor coupled to the second storage gate, and a capacitor coupled to the floating diffusion through a third transistor. The image sensor pixel may output image signals associated with the first charge generated by the photodiode for the first image frame while the photodiode concurrently generates the second charge for the second image frame. The second storage gate may be used to store overflow charge. Overflow charge for the second frame may be stored at the second storage gate while image signals associated with the first image frame are read out from capacitor and the floating diffusion.

Claims

1. An image sensor pixel, comprising:

a photodiode that generates charge in response to incident light;

a first storage gate coupled to the photodiode, wherein the first storage gate comprises a first charge storage region;

a second storage gate coupled to the photodiode, wherein the second storage gate comprises a second charge storage region;

first, second, and third transistors;

a floating diffusion region coupled to the first storage gate through the first transistor; and

a capacitor coupled to the second charge storage region of the second storage gate through the second transistor, wherein the capacitor is coupled to the floating diffusion region through the third transistor, and wherein the third transistor has first and second terminals, the first transistor being coupled to the first terminal of the third transistor and the second transistor being coupled to the second terminal of third transistor.

2. The image sensor pixel defined in claim 1, wherein a circuit node is coupled between the second transistor, the third transistor, and the capacitor, the image sensor pixel further comprising:

a reset transistor coupled between a power supply voltage source and the circuit node, wherein the capacitor is coupled between the circuit node and the power supply voltage source.

3. The image sensor pixel defined in claim 2, wherein the first, second, third, and reset transistors are controlled using respective first, second, third, and reset control signals, wherein the reset control signal is adjusted to reset the capacitor using the power supply voltage source, and wherein the third control signal is asserted concurrently with adjusting the reset signal to reset the floating diffusion region using the power supply voltage source.

4. The image sensor pixel defined in claim 2, further comprising:

a source follower transistor having a gate terminal coupled to the floating diffusion region, a first terminal coupled to a pixel readout line via a row select transistor, and a second terminal coupled to the capacitor and the power supply voltage source.

5. The image sensor pixel defined in claim 1, wherein the first storage gate comprises a fourth transistor with a first gate terminal that receives a first control signal and the first charge storage region is formed from doped semiconductor, and wherein the second storage gate comprises a fifth transistor with a second gate terminal that receives a second control signal and the second charge storage region is formed from doped semiconductor.

6. The image sensor pixel defined in claim 1, wherein the second storage gate is configured to store an overflow charge generated by the photodiode and wherein the first storage gate is configured to store a remaining charge that remains on the photodiode after the overflow charge has been transferred to the second storage gate.

7. The image sensor pixel defined in claim 6, wherein the second and third transistors are configured to transfer the overflow charge from the second storage gate onto the capacitor and the floating diffusion region.

8. The image sensor pixel defined in claim 7, wherein the image sensor pixel is configured to output a low gain image signal associated with the overflow charge transferred onto the capacitor and the floating diffusion region, and wherein the first and third transistors are configured to transfer the remaining charge from the first storage gate onto the floating diffusion region and the capacitor after the low gain image signal has been output by the image sensor pixel.

9. The image sensor pixel defined in claim 8, wherein the image sensor pixel is configured to output a high gain image signal associated with the remaining charge transferred onto the floating diffusion and the capacitor.

10. The image sensor pixel defined in claim 9, wherein the photodiode is configured to generate the remaining charge and the overflow charge during an exposure time associated with a given image frame, and wherein the photodiode is configured to generate additional charge during a subsequent exposure time associated with a subsequent image frame while the low gain image signal is being output by the image sensor pixel.

11. The image sensor pixel defined in claim 1, wherein the photodiode is configured to generate the charge during an exposure time associated with a given image frame and wherein the first and second storage gates are configured to store portions of the generated charge during a series of alternating shorter integration times that are distributed over time throughout the exposure time associated with the given image frame.

12. An image sensor pixel, comprising:

a photodiode that generates charge in response to incident light;

a first storage gate coupled to the photodiode;

a second storage gate coupled to the photodiode;

a first charge transfer transistor coupled to the photodiode through the first charge storage gate;

a second charge transfer transistor coupled to the photodiode through the second charge storage gate;

a photodiode reset transistor coupled to the photodiode;

a floating diffusion region coupled to the first storage gate through the first charge transfer transistor, wherein the second storage gate is operable to store an overflow charge generated by the photodiode and wherein the first storage gate is operable to store a remaining charge that remains on the photodiode after the overflow charge has been transferred to the second storage gate;

a gain selection transistor coupled to the floating diffusion region; and

a capacitor coupled to the floating diffusion region through the gain selection transistor.

13. The image sensor pixel defined in claim 12, wherein second charge transfer transistor is coupled to the capacitor and wherein the second charge transfer transistor is coupled to the floating diffusion region through the gain selection transistor.

14. The image sensor pixel defined in claim 13, wherein a circuit node is coupled between the second charge transfer transistor, the gain selection transistor, and the capacitor, the capacitor is coupled between the circuit node and a power supply voltage, and the image sensor pixel further comprises:

a reset transistor coupled between the circuit node and the power supply voltage in parallel with the capacitor.

15. The image sensor pixel defined in claim 12, wherein the second charge transfer transistor is coupled to the floating diffusion region and wherein the second charge transfer transistor is coupled to the capacitor through the gain selection transistor.

16. The image sensor pixel defined in claim 15, wherein the capacitor is coupled between the gain selection transistor and a power supply voltage, the image sensor pixel further comprising:

a reset transistor coupled between the power supply voltage and the floating diffusion region.

17. The image sensor pixel defined in claim 12, wherein the photodiode is operable to generate a first charge for a first image frame and a second charge for a second image frame subsequent to the first image frame, wherein the image sensor pixel is operable to output image signals associated with the first charge generated by the photodiode for the first image frame onto a pixel readout path while the photodiode concurrently generates the second charge for the second image frame.

18. The image sensor pixel defined in claim 17, wherein the first charge comprises the overflow charge and the remaining charge, wherein at least the second transistor is operable to transfer the overflow charge to the capacitor, wherein the second storage gate is operable to store an overflow portion of the second charge after the overflow charge of the first charge has been transferred to the capacitor and while at least some of the image signals associated with the first charge are concurrently output onto the pixel readout path by the image sensor pixel.

19. A method of operating an image sensor pixel having a photodiode, a floating diffusion region, a capacitor, a first storage gate coupled to the photodiode, a second storage gate coupled to the photodiode, a first transistor coupled between the first storage gate and a floating diffusion region, a second transistor coupled to the second storage gate, and a third transistor coupled between the capacitor and the floating diffusion region, the method comprising:

with the photodiode, integrating a first charge for a given image frame;

with the second storage gate, storing an overflow portion of the first charge for the given image frame;

with the second and third transistors, transferring the overflow portion of the first charge to the capacitor and the floating diffusion region;

with the first storage gate, storing a remaining portion of the first charge after the overflow portion of the first charge has been transferred to the capacitor and the floating diffusion region;

with the photodiode, integrating a second charge for a subsequent image frame while an image signal associated with the transferred overflow portion of the first charge is concurrently read out from the image sensor pixel; and

with the second storage gate, storing an overflow portion of the second charge for the subsequent image frame while the image signal associated with the transferred overflow portion of the first charge is concurrently read out from the image sensor pixel.