Platform power consumption reduction via power state switching

• US 10,564,705 B2
• Filed: 05/18/2018
• Issued: 02/18/2020
• Est. Priority Date: 12/26/2012
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Muralidhar, Rajeev D., Seshadri, Harinarayanan, Rudramuni, Vishwesh M., Quinzio, Richard, Fiat, Christophe, Zayet, Aymen, Singh, Youvedeep, Mansoor, Illyas M.
• Primary Examiner(s): Yanchus, III, Paul B
• Application Number:
  US15/984,185
• Publication Number:
  US 20180364792A1
• Time in Patent Office: 641 Days
• Field of Search: None
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

Claims

1. An apparatus comprising:

control logic, the control logic at least partially comprising hardware logic, to cause a processor to enter a first low power consumption state instead of a second low power consumption state based on a threshold time period between a first wake event and a second wake event,

wherein the first low power consumption state is to consume more power than the second low power consumption state, wherein the first wake event or the second wake event are to each correspond to one of a plurality of awake requests, wherein the processor is to enter the first low power consumption state based at least in part on one of the plurality of awake requests, wherein each of the plurality of awake requests is to cause prevention of entry into the second low power consumption state for as long as the one or more awake requests are active.

2. The apparatus of claim 1, wherein each of the plurality of awake requests causes one or more platform resources to stay powered on or awake.

3. The apparatus of claim 1, wherein the plurality of awake requests are to be generated in response to one or more requests from one of an application and a service.

4. The apparatus of claim 1, wherein the first wake event is to correspond to a first one of the plurality of awake requests and the second wake event is to correspond to a second one of the plurality of awake requests.

5. The apparatus of claim 1, wherein the control logic is to cause the processor to enter the first low power consumption state based on a source of the first wake event or second wake event.

6. The apparatus of claim 1, further comprising memory to store operating system software, wherein the operating system software is to trigger the first wake event or second wake event.

7. The apparatus of claim 6, wherein the operating system software is to trigger the first wake event or the second wake event based on a timer.

8. The apparatus of claim 1, wherein the control logic is to determine whether the processor is to enter the first low power consumption state based on one or more of workload, and usage conditions in a platform that comprises the processor.

9. The apparatus of claim 1, wherein the second low power consumption state comprises an idle state or a standby state.

10. The apparatus of claim 1, further comprising memory to store application software, wherein the application software is to trigger the first wake event or second wake event.

11. The apparatus of claim 10, wherein the application software is to trigger the first or second wake event based on a timer.

12. The apparatus of claim 1, wherein the first or second wake event is to indicate resumption from a platform idle state.

13. The apparatus of claim 1, wherein the processor is to comprise a plurality of processor cores, wherein at least the first wake event or the second wake event is to cause at least one of the plurality of the processor cores to wake from the first or second low power consumption state.

14. The apparatus of claim 1, wherein the threshold time period is about 60 seconds.

15. A method comprising:

determining whether a threshold time period exists between a first wake event and a second wake event;

causing a processor to enter a first low power consumption state instead of a second low power consumption state based on the existence of the threshold time period,

wherein the first low power consumption state is to consume more power than the second low power consumption state, wherein the processor enters the first low power consumption state based on one of the plurality of awake requests, wherein each of the plurality of awake requests causes prevention of entry into the second low power consumption state for as long as the one or more awake requests are active.

16. The method of claim 15, further comprising determining whether one or more awake requests exist, wherein the first wake event corresponds to the first one of the one or more awake requests and the second wake event corresponds to a second one of the one or more awake requests.

17. The method of claim 15, further comprising causing the processor to enter the first low power consumption state based on a source of the first wake event or second wake event.

18. A non-transitory computer-readable medium to store instructions that when executed by a processor cause the processor to:

determine whether a threshold time period exists between a first wake event and a second wake event;

cause the processor to enter a first low power consumption state instead of a second low power consumption state based on the existence of the threshold time period,

wherein the first low power consumption state is to consume more power than the second low power consumption state, wherein the first wake event or the second wake event are to each correspond to one of a plurality of awake requests, wherein the processor is to enter the first low power consumption state based on one of the plurality of awake requests, wherein each of the plurality of awake requests is to cause prevention of entry into the second low power consumption state for as long as the one or more awake requests are active.

19. The non-transitory computer-readable medium of claim 18, wherein each of the plurality of awake requests is to cause one or more platform resources to stay powered on or awake.

20. The non-transitory computer-readable medium of claim 18, wherein the instructions are to cause the processor to generate one or more awake requests in response to one or more requests from one of an application and a service.

21. The non-transitory computer-readable medium of claim 18, wherein the instructions are to cause the processor to enter the first low power consumption state based on a source of the first wake event or second wake event.

22. The non-transitory computer-readable medium of claim 18, wherein the non-transitory computer-readable memory is to store operating system software, wherein the operating system software is to trigger the first wake event or second wake event.

23. The non-transitory computer-readable medium of claim 22, wherein the operating system software is to trigger the first wake event or the second wake event based on a timer.

24. The non-transitory computer-readable medium of claim 18, wherein the instructions are to cause the processor to determine whether the processor is to enter the first low power consumption state based on one or more of workload, and usage conditions in a platform that comprises the processor.

25. The non-transitory computer-readable medium of claim 18, wherein the second low power consumption state comprises an idle state or a standby state.