Detecting and reporting unintended state changes
First Claim
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1. A computer-implemented method for testing hardware, the method comprising:
- reading, by a processor, a stream of test instructions;
determining, by the processor, test instruction exceptions present in the stream of test instructions;
inserting, by the processor, an interrupt for each determined test instruction exception;
generating, by the processor, one or more error messages for each determined test instruction exception;
inputting, by the processor, the stream of test instructions to test the hardware;
inputting, by the processor, the stream of test instructions to a test instruction simulator; and
comparing results of the stream of test instructions input to the hardware with results of the stream of test instructions input to the test instruction simulator to determine if the hardware is operating in the same manner as the test instruction simulator.
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Abstract
Embodiments of the invention are directed to computer-implemented methods, computer systems, and computer program products for testing hardware. The method includes reading a stream of test instructions. The method further includes determining if test instruction exceptions present in the stream of test instructions. The method further includes inserting an interrupt into the test instruction stream for each determined test instruction exception. The method further includes generating one or more error messages for each determined test instruction exception.
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Citations
5 Claims
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1. A computer-implemented method for testing hardware, the method comprising:
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reading, by a processor, a stream of test instructions; determining, by the processor, test instruction exceptions present in the stream of test instructions; inserting, by the processor, an interrupt for each determined test instruction exception; generating, by the processor, one or more error messages for each determined test instruction exception; inputting, by the processor, the stream of test instructions to test the hardware; inputting, by the processor, the stream of test instructions to a test instruction simulator; and comparing results of the stream of test instructions input to the hardware with results of the stream of test instructions input to the test instruction simulator to determine if the hardware is operating in the same manner as the test instruction simulator. - View Dependent Claims (2, 3, 4, 5)
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Specification
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsGomes, Louis P.
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Primary Examiner(s)Riad, Amine
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Application NumberUS15/805,738Publication NumberTime in Patent Office833 DaysField of SearchUS Class CurrentCPC Class CodesG06F 11/2268 Logging of test resultsG06F 11/261 by simulating additional ha...G06F 11/263 Generation of test inputs, ...
