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Detecting and reporting unintended state changes

  • US 10,565,078 B2
  • Filed: 11/07/2017
  • Issued: 02/18/2020
  • Est. Priority Date: 06/30/2017
  • Status: Active Grant
First Claim
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1. A computer-implemented method for testing hardware, the method comprising:

  • reading, by a processor, a stream of test instructions;

    determining, by the processor, test instruction exceptions present in the stream of test instructions;

    inserting, by the processor, an interrupt for each determined test instruction exception;

    generating, by the processor, one or more error messages for each determined test instruction exception;

    inputting, by the processor, the stream of test instructions to test the hardware;

    inputting, by the processor, the stream of test instructions to a test instruction simulator; and

    comparing results of the stream of test instructions input to the hardware with results of the stream of test instructions input to the test instruction simulator to determine if the hardware is operating in the same manner as the test instruction simulator.

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