Methods and systems for managing synonyms in virtually indexed physically tagged caches

• US 10,565,113 B2
• Filed: 08/13/2015
• Issued: 02/18/2020
• Est. Priority Date: 10/18/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Avudaiyappan, Karthikeyan
• Primary Examiner(s): Krofcheck, Michael
• Application Number:
  US14/825,502
• Publication Number:
  US 20160224471A1
• Time in Patent Office: 1,650 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/1054 the data cache being concurrently physically addressed
• CPC Class Codes: G06F 12/1063 the data cache being concurrently virtually addressed
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

Methods and systems for managing synonyms in VIPT caches are disclosed. A method includes tracking lines of a copied cache using a directory, examining a specified bit of a virtual address that is associated with a load request and determining its status and making an entry in one of a plurality of parts of the directory based on the status of the specified bit of the virtual address that is examined. The method further includes updating one of, and invalidating the other of, a cache line that is associated with the virtual address that is stored in a first index of the copied cache, and a cache line that is associated with a synonym of the virtual address that is stored at a second index of the copied cache, upon receiving a request to update a physical address associated with the virtual address.

Claims

1. A non-transitory computer readable medium having stored therein a set of instructions, which when executed by a computing device cause the computing device to perform a set of operations, the operations comprising:

tracking lines of level 1 cache that are copied to a level 2 cache using a directory in a cache controller of the level 2 cache;

examining a specified bit of a virtual address that is associated with a load request at the cache controller and determining its status;

making an entry in one of a plurality of parts of said directory based on the status of the specified bit of the virtual address that is examined; and

changing, in a single clock cycle, only a data value, of one of, and invalidating the other of in the single clock cycle, a cache line that is associated with said virtual address that is stored in a first index of the level 2 cache, and a cache line that is associated with a synonym of said virtual address that is stored at a second index of the level 2 cache, upon receiving a request to update a physical address associated with said virtual address, where the synonym is another virtual address that maps to the physical address of a memory component.

2. The non-transitory computer readable medium of claim 1 wherein said virtual address and said synonym is identified in said directory before said invalidating.

3. The non-transitory computer readable medium of claim 1 wherein making said entry in said directory comprises placing said entry in one of a first and a second panel based on said specified bit of said virtual address.

4. The non-transitory computer readable medium of claim 1 wherein said cache line associated with said virtual address stored in said first index of the level 2 cache, and said cache line associated with said synonym stored at said second index of the level 2 cache reside at said first and said second index until a request to update said physical address associated with said virtual address is made.

5. The non-transitory computer readable medium of claim 1 wherein said invalidating of said one of said first cache line that is associated with said virtual address that is stored in a first index of the level 2 cache, and said second cache line that is associated with said synonym, is determined randomly.

6. The non-transitory computer readable medium of claim 1 further comprising receiving said load request from a level 2 cache pipeline.

7. The non-transitory computer readable medium of claim 1 wherein said directory comprises a first and a second panel that correspond to first and second virtual address ranges.

8. The non-transitory computer readable medium of claim 1 wherein the level 2 cache is a copy of a level 1 cache.

9. The non-transitory computer readable medium of claim 1 wherein said cache system is a virtually indexed physically tagged (VIPT) system.

10. A cache memory system, comprising:

memory components including a main memory, a level 1 cache and a level 2 cache; and

a memory controller in the level 2 cache, wherein said memory controller includes a system for managing synonyms that comprises;

a tracking component that tracks copied lines of the level 1 cache in the level 2 cache using a directory;

an examining component that examines a specified bit of a virtual address that is associated with a load request and determining its status;

an entry making component that makes an entry in one of a plurality of parts of said directory based on the status of the specified bit of the virtual address that is examined; and

a cache line updating and invalidating component that changes only a data value, in a single clock cycle, of one of, and invalidates the other of in the single clock cycle, a cache line in the level 2 cache that is associated with said virtual address that is stored in a first index of the level 2 cache, and a cache line that is associated with a synonym of said virtual address that is stored at a second index of the level 2 cache, upon receiving a request to update a physical address associated with said virtual address, where the synonym is another virtual address that maps to the physical address in the main memory.

11. The cache memory system of claim 10 wherein said cache line updating and invalidating component identifies said virtual address and said synonym in said directory before said changing and said invalidating.

12. The cache memory system of claim 10 wherein said entry making component places said entry in one of a first and a second panel based on said specified bit of said virtual address.

13. The cache memory system of claim 10 wherein said cache line updating and invalidating component allows said cache line associated with said virtual address stored in said first index of the level 2 cache, and said cache line associated with said synonym stored at said second index of the level 2 cache to reside at said first and said second index until a request to update said physical address associated with said virtual address is made.

14. The cache memory system of claim 10 wherein said cache line updating and invalidating component determines randomly said changing and said invalidating of said one of said cache line that is associated with said virtual address that is stored in a first index of the level 2 cache, and said cache line that is associated with said synonym.

15. The cache memory system of claim 10 wherein said examining component examines load requests from a level 2 cache pipeline.

16. The cache memory system of claim 10 wherein level 2 cache is a copy of the level 1 cache.

17. The cache memory system of claim 10 wherein said cache system is a virtually indexed physically tagged (VIPT) system.