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Hybrid logical to physical address translation for non-volatile storage devices with integrated compute module

  • US 10,565,123 B2
  • Filed: 10/05/2017
  • Issued: 02/18/2020
  • Est. Priority Date: 04/10/2017
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a memory system, comprising;

    non-volatile memory;

    working memory separate from the non-volatile memory, the working memory is configured to store a coarse logical address to physical address table for use with data stored in the non-volatile memory as sequentially accessed data and a fine logical address to physical address table for use with data stored in the non-volatile memory as randomly accessed data;

    a controller in communication with the non-volatile memory and the working memory, the controller includes a processor, the controller is configured to create data for the coarse logical address to physical address table by reading fine logical address to physical address data and reducing the fine logical address to physical address data to coarse logical address to physical address data, the controller is configured to;

    randomly access data stored in the non-volatile memory as randomly accessed data in response to a request from a host by translating a logical address from the host to a physical address in the non-volatile memory using the fine logical address to physical address table in the working memory,sequentially access data stored in the non-volatile memory as sequentially accessed data in response to a request from the host by translating a logical address from the host to a physical address in the non-volatile memory using the coarse logical address to physical address table in the working memory, andrandomly access data stored in the non-volatile memory as sequentially accessed data in response to a request from the host by translating a logical address from the host to a physical address in the non-volatile memory using the coarse logical address to physical address table in the working memory; and

    a compute engine positioned within the memory system, the compute engine is in communication with the controller and the working memory, the compute engine is different than the processor included in the controller, the compute engine is configured to receive code from the host and perform one or more database operations on target data in the non-volatile memory by executing the code and using the working memory.

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