Hybrid logical to physical address translation for non-volatile storage devices with integrated compute module
First Claim
1. An apparatus, comprising:
- a memory system, comprising;
non-volatile memory;
working memory separate from the non-volatile memory, the working memory is configured to store a coarse logical address to physical address table for use with data stored in the non-volatile memory as sequentially accessed data and a fine logical address to physical address table for use with data stored in the non-volatile memory as randomly accessed data;
a controller in communication with the non-volatile memory and the working memory, the controller includes a processor, the controller is configured to create data for the coarse logical address to physical address table by reading fine logical address to physical address data and reducing the fine logical address to physical address data to coarse logical address to physical address data, the controller is configured to;
randomly access data stored in the non-volatile memory as randomly accessed data in response to a request from a host by translating a logical address from the host to a physical address in the non-volatile memory using the fine logical address to physical address table in the working memory,sequentially access data stored in the non-volatile memory as sequentially accessed data in response to a request from the host by translating a logical address from the host to a physical address in the non-volatile memory using the coarse logical address to physical address table in the working memory, andrandomly access data stored in the non-volatile memory as sequentially accessed data in response to a request from the host by translating a logical address from the host to a physical address in the non-volatile memory using the coarse logical address to physical address table in the working memory; and
a compute engine positioned within the memory system, the compute engine is in communication with the controller and the working memory, the compute engine is different than the processor included in the controller, the compute engine is configured to receive code from the host and perform one or more database operations on target data in the non-volatile memory by executing the code and using the working memory.
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Abstract
A host compiles code to perform a set of one or more database operations on target and embeds an indication of whether the target data is randomly accessed data or sequentially accessed data. The compiled code is transmitted to the compute engine inside a memory system that maintains a first portion of memory for storing sequentially accessed data and a second portion of memory for storing randomly accessed data. The memory system (e.g. SSD) maintains reduced size L2P tables in volatile working memory by maintaining coarse L2P tables in the working memory for use with sequentially accessed data and maintaining fine L2P tables in the working memory for use with randomly accessed data. The compute engine uses the compiled code to perform the set of one or more database operations on the target data using the working memory.
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Citations
19 Claims
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1. An apparatus, comprising:
a memory system, comprising; non-volatile memory; working memory separate from the non-volatile memory, the working memory is configured to store a coarse logical address to physical address table for use with data stored in the non-volatile memory as sequentially accessed data and a fine logical address to physical address table for use with data stored in the non-volatile memory as randomly accessed data; a controller in communication with the non-volatile memory and the working memory, the controller includes a processor, the controller is configured to create data for the coarse logical address to physical address table by reading fine logical address to physical address data and reducing the fine logical address to physical address data to coarse logical address to physical address data, the controller is configured to; randomly access data stored in the non-volatile memory as randomly accessed data in response to a request from a host by translating a logical address from the host to a physical address in the non-volatile memory using the fine logical address to physical address table in the working memory, sequentially access data stored in the non-volatile memory as sequentially accessed data in response to a request from the host by translating a logical address from the host to a physical address in the non-volatile memory using the coarse logical address to physical address table in the working memory, and randomly access data stored in the non-volatile memory as sequentially accessed data in response to a request from the host by translating a logical address from the host to a physical address in the non-volatile memory using the coarse logical address to physical address table in the working memory; and a compute engine positioned within the memory system, the compute engine is in communication with the controller and the working memory, the compute engine is different than the processor included in the controller, the compute engine is configured to receive code from the host and perform one or more database operations on target data in the non-volatile memory by executing the code and using the working memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method, comprising:
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storing data written as sequentially accessed data in non-volatile memory of a memory system; storing data written as randomly accessed data in the non-volatile memory of the memory system; maintaining one or more logical to physical (L2P) tables in the non-volatile memory of the memory system for translating logical addresses to physical addresses for the stored data written as sequentially accessed data in the non-volatile memory of the memory system and for translating logical addresses to physical addresses for the stored data written as randomly accessed data in the non-volatile memory of the memory system; maintaining a coarse L2P cache in a volatile working memory of the memory system to store a subset of entries in the one or more L2P tables for translating logical addresses to physical addresses for the stored data written as sequentially accessed data in the non-volatile memory of the memory system; maintaining a fine L2P cache in the volatile working memory of the memory system to store a subset of entries in the one or more L2P tables for translating logical addresses to physical addresses for the stored data written as randomly accessed data in the non-volatile memory of the memory system; creating data for the coarse L2P cache in the volatile working memory by reading fine L2P data from the one or more L2P tables, reducing the fine L2P data to coarse L2P data and storing the coarse L2P data in the coarse L2P cache; receiving, by the memory system from a host, code that includes instructions for programming a compute engine within the memory system to perform a set of one or more database operations on target data in the non-volatile memory of the memory system; executing, by the compute engine inside the memory system, the code to perform the set of one or more database operations on the target data using the volatile working memory; and performing an address translation for a logical address associated with the one or more database operations using the coarse L2P cache or the fine L2P cache. - View Dependent Claims (16, 17, 18)
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19. A memory system, comprising:
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non-volatile memory configured to store a database comprising leaf nodes and branch nodes pointing to the leaf nodes in blocks of memory cells, the blocks of memory cells are divided into pages, the non-volatile memory comprises a first set of memory cells configured to store the branch nodes of the database as randomly accessed data in pages and a second set of memory cells configured to store the leaf nodes of the database as sequentially accessed data in pages; working memory separate from the non-volatile memory; and a controller in communication with the non-volatile memory and the working memory, the controller including a host interface and a processor, the controller being configured to; store a first logical address to physical address table in the working memory for accessing the branch nodes in the first set of memory cells and a second logical address to physical address table in the working memory for accessing the leaf nodes in the second set of memory cells, the first logical address to physical address table and the second logical address to physical address table are separate from the database, create data for the second logical address to physical address table by reading fine logical address to physical address data and reducing the fine logical address to physical address data to coarse logical address to physical address data receive a request from a host via the host interface, the request including an indication of target data of the database to be accessed, access the target data from the first set of memory cells using the first logical address to physical address table in response to the request if the target data is randomly accessed data, and access the target data from the second set of memory cells using the second logical address to physical address table in response to the request if the target data is sequentially accessed data; and a compute engine that is behind the host interface and is in communication with the controller and the working memory, the compute engine is separate from the processor of the controller, the compute engine being configured to perform data manipulation operations on sequentially accessed data stored in the second set of memory cells using the working memory to store working data for the compute engine while performing the data manipulation operations.
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Specification