Targeted delay optimization through programmable clock delays

• US 10,565,334 B1
• Filed: 12/20/2017
• Issued: 02/18/2020
• Est. Priority Date: 12/20/2017
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lu, Ruibing, Das, Sabyasachi
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US15/849,216
• Time in Patent Office: 790 Days
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G06F 11/323 Visualisation of programs or trace data
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/396 Clock trees

Abstract

Disclosed approaches for processing a circuit design include determining first slacks of cells, including a target cell, coupled to receive a clock signal through a first clock leaf. The first slacks are based on a current delay value specified for a first programmable delay circuit. The method predicts second slacks of the cells based on another delay value specified for the first programmable delay circuit, and then determines whether or not the second slacks indicate a degradation in timing relative to the first slacks. The current delay value of the first programmable delay circuit is adjusted to the other delay value in response to determining the second slacks indicates no degradation in timing. The target cell is reconnected to receive the clock signal from a second clock leaf having a second programmable delay circuit specified with the other delay value in response to determining the second slacks indicates degradation in timing.

Claims

1. A computer-implemented method of processing a circuit design, comprising:

performing operations on a processor including;

determining a timing violation of a target cell coupled to receive a clock signal through a first clock leaf of a plurality of clock leaves of the circuit design;

determining a first set of slacks of a plurality of cells, including the target cell, coupled to receive the clock signal through the first clock leaf, wherein slacks of the first set are based on a current delay value specified for a first programmable delay circuit of the first clock leaf;

predicting a second set of slacks of the cells based on another delay value specified for the first programmable delay circuit of the first clock leaf, wherein the other delay value is sufficient to resolve the timing violation of the target cell;

determining whether or not the second set of slacks indicates a degradation in timing relative to the first set of slacks;

adjusting the current delay value of the first programmable delay circuit of the first clock leaf to the other delay value in response to determining the second set of slacks indicates no degradation in timing relative to the first set of slacks; and

reconnecting the target cell to receive the clock signal from a second clock leaf having a second programmable delay circuit specified with the other delay value in response to determining the second set of slacks indicates degradation in timing relative to the first set of slacks.

2. The method of claim 1, wherein prior to the reconnecting of the target cell to the second clock leaf, one or more cells other than the plurality of cells are coupled to receive the clock signal through the second clock leaf.

3. The method of claim 1, wherein the reconnecting the target cell includes:

instantiating the second clock leaf in the circuit design in response to determining the second set of slacks indicates degradation in timing relative to the first set of slacks; and

reconnecting the target cell to receive the clock signal from the instantiated second clock leaf.

4. The method of claim 1, further comprising:

placing and routing the circuit design; and

wherein the determining the first set of slacks, the predicting the second set of slacks, the determining the degradation in timing relative to the first set of slacks, and the adjusting are performed by the processor subsequent to the placing and routing.

5. The method of claim 1, wherein in response to the target cell being an end point cell of a setup critical timing path:

the adjusting the current delay value to the other delay value includes adjusting the current delay value to an adjusted delay value that is greater than the current delay value; and

the reconnecting the target cell includes reconnecting the target cell to receive the clock signal through the second clock leaf having the second programmable delay circuit specified with a delay value greater than the current delay value.

6. The method of claim 1, wherein in response to the target cell being an end point cell of a hold critical timing path:

the adjusting the current delay value to the other delay value includes adjusting the current delay value to an adjusted delay value that is less than the current delay value; and

the reconnecting the target cell includes reconnecting the target cell to receive the clock signal through the second clock leaf having the second programmable delay circuit specified with a delay value less than the current delay value.

7. The method of claim 1, wherein in response to the target cell being a starting point cell of a setup critical timing path:

the adjusting the current delay value to the other delay value includes adjusting the current delay value to an adjusted delay value that is less than the current delay value; and

the reconnecting the target cell includes reconnecting the target cell to receive the clock signal through the second clock leaf having the second programmable delay circuit specified with a delay value that is less than the current delay value.

8. The method of claim 1, wherein in response to the target cell being a starting point cell of a hold critical timing path:

the adjusting the current delay value to the other delay value includes adjusting the current delay value to an adjusted delay value that is greater than the current delay value; and

the reconnecting the target cell includes reconnecting the target cell to receive the clock signal through the second clock leaf having the second programmable delay circuit specified with a delay value that is greater than the current delay value.

9. The method of claim 1, further comprising:

identifying a critical timing path in the circuit design, wherein the target cell is on the critical timing path; and

selecting the other delay value that would reduce a timing violation of the critical timing path.

10. The method of claim 1, further comprising:

generating configuration data from the circuit design; and

configuring a programmable IC with the configuration data.

11. A computer-implemented method of processing a circuit design, comprising:

performing operations on a programmed processor including;

identifying one or more critical timing paths having respective timing violations based on a first frequency of a clock signal, wherein a respective target cell on each critical timing path is coupled to receive the clock signal through a first clock leaf of a plurality of clock leaves of the circuit design;

for each respective target cell of the one or more critical timing paths, performing operations including;

determining a first set of slacks of a plurality of cells, including the target cell, coupled to receive the clock signal through the first clock leaf, wherein the slacks of the first set are based on a current delay value specified for a first programmable delay circuit of the first clock leaf;

predicting a second set of slacks of the plurality of cells based on another delay value specified for the first programmable delay circuit, wherein the other delay value is sufficient to resolve the respective timing violation;

determining whether or not the second set of slacks indicates a degradation in timing relative to the first set of slacks;

adjusting the current delay value of the first programmable delay circuit to the other delay value in response to determining the second set of slacks indicates no degradation in timing relative to the first set of slacks; and

reconnecting the target cell to receive the clock signal through a second clock leaf having a second programmable delay circuit specified with the other delay value in response to determining the second set of slacks indicates degradation in timing relative to the first set of slacks; and

repeating the identifying and the performing operations for each respective target cell for a second frequency of the clock signal that is greater than the first frequency.

12. The method of claim 11, wherein in response to a respective target cell being an end point cell of the setup critical timing paths:

the adjusting the current delay value to the other delay value includes adjusting the current delay value to a delay value that is greater than the current delay value; and

the reconnecting the target cell includes reconnecting the target cell to receive the clock signal through the second clock leaf having the second programmable delay circuit specified with a delay value greater than the current delay value.

13. The method of claim 11, wherein in response to a respective target cell being an end point cell of the hold critical timing paths:

the adjusting the current delay value to the other delay value includes adjusting the current delay value to a delay value that is less than the current delay value; and

the reconnecting the target cell includes reconnecting the target cell to receive the clock signal through the second clock leaf having the second programmable delay circuit specified with a delay value less than the current delay value.

14. The method of claim 11, wherein in response to a respective target cell being a starting point cell of the setup critical timing paths:

the adjusting the current delay value to the other delay value includes adjusting the current delay value to an adjusted delay value that is less than the current delay value; and

the reconnecting the target cell includes reconnecting the target cell to receive the clock signal through the second clock leaf having the second programmable delay circuit specified with a delay value less than the current delay value.

15. The method of claim 11, wherein in response to a respective target cell being a starting point cell of the hold critical timing paths:

the adjusting the current delay value to the other delay value includes adjusting the current delay value to an adjusted delay value that is greater than the current delay value; and

the reconnecting the target cell includes reconnecting the target cell to receive the clock signal through the second clock leaf having the second programmable delay circuit specified with a delay value greater than the current delay value.

16. The method of claim 11, further comprising:

generating configuration data from the circuit design; and

configuring a programmable IC with the configuration data.

17. A system, comprising:

a computer system including;

a processor; and

a memory configured with instructions that when executed by the processor cause the processor to perform operations including;

determining a timing violation of a target cell coupled to receive a clock signal through a first clock leaf of a plurality of clock leaves of the circuit design;

determining a first set of slacks of a plurality of cells, including the target cell, coupled to receive the clock signal through the first clock leaf, wherein slacks of the first set are based on a current delay value specified for a first programmable delay circuit of the first clock leaf;

predicting a second set of slacks of the cells based on another delay value specified for the first programmable delay circuit, wherein the other delay value is sufficient to resolve the timing violation of the target cell;

determining whether or not the second set of slacks indicates a degradation in timing relative to the first set of slacks;

adjusting the current delay value of the first programmable delay circuit to the other delay value in response to determining the second set of slacks indicates no degradation in timing relative to the first set of slacks; and

reconnecting the target cell to receive the clock signal from a second clock leaf having a second programmable delay circuit specified with the other delay value, in response to determining the second set of slacks indicate degradation in timing relative to the first set of slacks.

18. The system of claim 17, wherein one or more cells other than the plurality of cells are coupled to receive the clock signal through the second clock leaf prior to the reconnecting of the target cell to the second clock leaf.

19. The system of claim 17, wherein the memory is configured with instructions that when executed by the processor cause the processor to perform operations including:

instantiating the second clock leaf in the circuit design in response to determining the second set of slacks indicates degradation in timing relative to the first set of slacks; and

reconnecting the target cell to receive the clock signal from the instantiated second clock leaf.

20. The system of claim 17, wherein the memory is configured with instructions that when executed by the processor cause the processor to perform operations including:

generating configuration data from the circuit design; and

configuring a programmable IC with the configuration data.