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Method of controlling on-die termination and system performing the same

  • US 10,566,038 B2
  • Filed: 03/12/2018
  • Issued: 02/18/2020
  • Est. Priority Date: 05/29/2017
  • Status: Active Grant
First Claim
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1. A method of operating a low power double data rate 5 (LPDDR5) dynamic random access memory (DRAM) in a multi-rank memory system including a plurality of memory ranks, the method comprising:

  • receiving a write command dedicated to a first memory rank among the plurality of memory ranks, wherein the write command conforms to an LPDDR5 standard and is not dedicated to a second memory rank among the plurality of memory ranks;

    enabling a reception buffer in the first memory rank;

    disabling a transmission driver in the first memory rank;

    disabling a reception buffer and a transmission driver in the second memory rank;

    receiving a data strobe signal pair;

    enabling on-die terminal (ODT) circuits of the first memory rank and the second memory rank in response to the write command;

    receiving data signals while the data strobe signal pair is toggled during the enabling of the ODT circuits of the first memory rank and the second memory rank;

    receiving a read command dedicated to the first memory rank, wherein the read command conforms to the LPDDR5 standard and is not dedicated to the second memory rank;

    enabling the transmission driver in the first memory rank;

    disabling the reception buffer in the first memory rank;

    disabling the reception buffer and the transmission driver in the second memory rank;

    disabling the ODT circuit of the first memory rank and enabling the ODT circuit of the second memory rank in response to the read command; and

    sending data signals while the data strobe signal pair is toggled during the disabling of the ODT circuit of the first memory rank and the enabling of the ODT circuit of the second memory rank.

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