Transistor structure having buried island regions

• US 10,566,192 B2
• Filed: 05/07/2015
• Issued: 02/18/2020
• Est. Priority Date: 05/07/2014
• Status: Active Grant

• Current Assignee: Finwave Semiconductor, Inc.
• Original Assignee: Cambridge Electronics, Inc.
• Inventors: Lu, Bin, Palacios, Tomas, Xia, Ling, Azize, Mohamed
• Primary Examiner(s): Hoang, Tuan A
• Application Number:
  US14/706,350
• Publication Number:
  US 20150349124A1
• Time in Patent Office: 1,748 Days
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/22 including, apart from doping materials or other impurities, only AIIBVI compounds
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/66462 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 : with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/861 : Diodes

Abstract

A semiconductor device such as a transistor includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions.

Claims

1. A semiconductor structure, comprising:

a source contact;

a drain contact;

a semiconductor region formed from a first Group-III nitride, the semiconductor region being located between the source and drain contacts;

a barrier layer located on the semiconductor region and formed from a second Group-III nitride, the barrier layer contacting the source and the drain, the barrier layer forming a heterostructure with the semiconductor region;

a plurality of island regions located in the semiconductor region and not in the barrier layer, the island regions each extending in a lateral direction and a second direction orthogonal to the lateral direction without extending to the source and drain contacts, the island regions extending in the lateral direction such that adjacent ones of the island regions are separated from one another by portions of the semiconductor region, each of the island regions differing from the semiconductor region and the barrier layer in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition;

a plurality of trenches each extending into the semiconductor region and through the barrier layer such that the barrier layer is excluded from the trenches, the island regions each being located at least at a bottom of a different one of the trenches; and

a gate electrode covering a least a portion of the island regions being located between the source and drain contacts; and

the island regions each extending beyond both a source-side and a drain-side of the gate electrode.

2. The semiconductor structure of claim 1 wherein the semiconductor region further includes at least one additional material and/or heterostructure.

3. The semiconductor structure of claim 1, wherein the second semiconductor layer is located on the semiconductor region and covers at least a portion of the island regions.

4. The semiconductor structure of claim 1, wherein the barrier layer has a recessed region under the gate electrode.

5. The semiconductor structure of claim 1 wherein a surface of the semiconductor region extends in a first plane and the island regions comprise a plurality of sub-layers, wherein an interface between each of the sub-layers extends in the first plane or a second plane orthogonal to the first plane, or at an angle with respect to the first plane that is different from 0 and 90 degrees.

6. The semiconductor structure of claim 1, wherein the gate electrode comprises one or more conductive materials selected from the group including metals, amorphous, polycrystalline, crystalline semiconductors or conductive oxides and dielectric materials.

7. The semiconductor structure of claim 1, further comprising one or more dielectric layers located between the conductive electrode and the surface of the semiconductor region.

8. The semiconductor structure of claim 7, wherein the dielectric layer comprises Al₂O₃, Si_xO_y, Si_xN_y, Si_xO_yN_z, Teflon, HfO₂, or any other dielectric with a dielectric constant below 200.

9. The semiconductor device of claim 1 wherein a top of the barrier layer is not flush with a top of the at least one island region.