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Systems and methods for dynamic semiconductor process scheduling

  • US 10,566,223 B2
  • Filed: 05/17/2017
  • Issued: 02/18/2020
  • Est. Priority Date: 08/28/2012
  • Status: Active Grant
First Claim
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1. A method comprising:

  • analyzing, by a computer program operating on a computer system, a plurality of expected times to complete each of a respective plurality of actions to be performed by a semiconductor processing tool comprising an expected time to transfer a first wafer from a wafer handling chamber to a first process module, an expected time to transfer the first wafer from the first process module to the wafer handling chamber, an expected time to transfer a second wafer from the wafer handling chamber to a second process module, and an expected time to transfer the second wafer from the second process module to the wafer handling chamber, the semiconductor processing tool including the first process module and the second process module; and

    automatically generating, by a computer program, a wafer processing plan based on the analysis, wherein the wafer processing plan, when executed by the processing tool, causes the semiconductor processing tool to;

    load the a first wafer into the first process module;

    load the a second wafer into the second process module;

    unload the first wafer from the first process module after loading the second wafer into the second process module;

    load a third wafer into the first process module after unloading the first wafer form the first process module; and

    unload the second wafer from the second process module after loading the third wafer into the first process module;

    wherein the semiconductor processing tool includes the wafer handling chamber in communication with the first process module and the second process module,wherein the computer program measures an actual time to complete the steps of load the first wafer, load the second wafer, unload the first wafer, load the third wafer, and unload the second wafer, and if the actual time exceeds a predetermined value, automatically adjusts future wafer processing plans based on the actual time to complete steps of load the first wafer, load the second wafer, unload the first wafer, load the third wafer, and unload the second wafer, andwherein the computer program distributes idle periods for the wafer handling chamber for before the step of unload the first wafer and after a step of unload the third wafer.

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