Semiconductor device and method for fabricating the same

• US 10,566,244 B2
• Filed: 08/01/2018
• Issued: 02/18/2020
• Est. Priority Date: 07/02/2018
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lee, Zhi-Cheng, Lee, Kai-Lin, Chen, Wei-Jen
• Primary Examiner(s): Pham, Thanhha S
• Application Number:
  US16/052,600
• Publication Number:
  US 20200006153A1
• Time in Patent Office: 566 Days
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.

Claims

1. A semiconductor device, comprising:

a substrate having a first region and a second region;

a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein the first fin-shaped structure and the second fin-shaped structure are disposed extending along a first direction;

a first single diffusion break (SDB) structure extending along a second direction on the first region to separate the first fin-shaped structure into a first portion and a second portion; and

a second SDB structure extending along the second direction on the second region to separate the second fin-shaped structure into a third portion and a fourth portion, wherein a top surface of the first SDB structure is higher than a top surface of the first fin-shaped structure while a top surface of the second SDB structure is even with a top surface of the second fin-shaped structure.

2. The semiconductor device of claim 1, wherein the first direction is orthogonal to the second direction.

3. The semiconductor device of claim 1, wherein the first SDB structure and the second SDB structure comprise different materials.

4. The semiconductor device of claim 1, further comprising:

a first gate structure on the first fin-shaped structure on the first region;

a second gate structure on the second fin-shaped structure on the second region;

a third gate structure on the second SDB structure on the second region; and

an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure.

5. The semiconductor device of claim 4, wherein top surfaces of the ILD layer, the first gate structure, the second gate structure, and the third gate structure are coplanar.

6. The semiconductor device of claim 4, wherein a top surface of the first SDB structure is even with a top surface of the ILD layer.

7. The semiconductor device of claim 4, wherein a top surface of the first SDB structure is even with top surfaces of the first gate structure, the second gate structure, and the third gate structure.

8. The semiconductor device of claim 1, wherein a top surface of the second SDB structure is even with a top surface of the second fin-shaped structure.