Method for enlarging tip portion of a fin-shaped structure

• US 10,566,327 B2
• Filed: 08/30/2017
• Issued: 02/18/2020
• Est. Priority Date: 08/03/2017
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Chun-Hao, Chen, Hsin-Yu, Hsieh, Shou-Wei
• Primary Examiner(s): Jahan, Bilkis
• Application Number:
  US15/691,703
• Publication Number:
  US 20190043858A1
• Time in Patent Office: 902 Days
• Field of Search: None
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin

Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

Claims

1. A semiconductor device, comprising:

a substrate having a first region and a second region;

a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion, a width of a bottom surface of the first fin-shaped structure is equal to a width of a bottom surface of the second fin-shaped structure, and a width of a top surface of the first fin-shaped structure is different from a width of a top surface of the second fin-shaped structure;

a shallow trench isolation (STI) around the bottom portions of the first fin-shaped structure and the second fin-shaped structure, wherein a bottom surface of the top portion of the first fin-shaped structure and a top surface of the bottom portion of the second fin-shaped structure are even with a top surface of the STI, the bottom surface of the top portion of the first fin-shaped structure is greater than a top surface of the bottom portion of the first fin-shaped structure, a bottom surface of the top portion of the second fin-shaped structure is less than the top surface of the bottom portion of the second fin-shaped structure, the bottom surface of the top portion of the second fin-shaped structure is less than the bottom surface of the top portion of the first fin-shaped structure, wherein a portion of the top surface of the STI is covered by the top portion of the first fin-shaped structure;

a first metal gate covering the top portion of the first fin-shaped structure; and

a second metal gate covering the top portion of the second fin-shaped structure.

2. The semiconductor device of claim 1, wherein a top surface of the top portion on the first region is greater than a top surface of the top portion on the second region.

3. The semiconductor device of claim 1, wherein a top surface of the bottom portion on the first region is equal to a top surface of the bottom portion on the second region.

4. The semiconductor device of claim 1, wherein the first region is a core region and the second region is an input/output region.