Methods used in forming integrated circuitry including forming first, second, and third contact openings
First Claim
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1. A method used in forming integrated circuitry, comprising:
- providing a substrate comprising first, second, and third electronic components that are laterally spaced from one another in a vertical cross-section;
the first electronic component comprising a first outer region comprising elemental-form silicon;
the second electronic component comprising a second outer region comprising metal material;
the third electronic component comprising a third outer region comprising elemental-form silicon directly above metal material;
insulative material being directly above the first, second, and third outer regions;
forming a first contact opening through the insulative material to the elemental-form silicon of the first outer region in the vertical cross-section while the second and third outer regions are completely covered with masking material in the vertical cross-section;
forming a second contact opening through the insulative material to the metal material of the second outer region in the vertical cross-section and a third contact opening through the insulative material to the elemental-form silicon of the third outer region in the vertical cross-section while the elemental-form silicon of the first outer region is completely covered with masking material in the vertical cross-section;
within the third contact opening and while the second contact opening is outwardly exposed, etching through the elemental-form silicon of the third outer region to the metal material of the third outer region selectively relative to the metal material of the second outer region;
the elemental-form silicon of the first outer region being completely covered with masking material in the vertical cross-section during said etching; and
after said etching, forming conductive material in the first, second, and third contact openings.
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Abstract
Integrated circuitry comprises a first conductive line buried within semiconductive material of a substrate. The first conductive line comprises conductively-doped semiconductor material directly above and directly against metal material in a vertical cross-section. A second conductive line is above the semiconductive material and is laterally-spaced from the first conductive line in the vertical cross-section. The second conductive line comprises metal material in the vertical cross-section. Insulative material is directly above the first and second conductive lines. A first conductive via extends through the insulative material and through the conductively-doped semiconductor material to the metal material of the first conductive line. A second conductive via extends through the insulative material to the metal material of the second conductive line. Other embodiments and aspects, including method, are disclosed.
8 Citations
23 Claims
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1. A method used in forming integrated circuitry, comprising:
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providing a substrate comprising first, second, and third electronic components that are laterally spaced from one another in a vertical cross-section;
the first electronic component comprising a first outer region comprising elemental-form silicon;
the second electronic component comprising a second outer region comprising metal material;
the third electronic component comprising a third outer region comprising elemental-form silicon directly above metal material;
insulative material being directly above the first, second, and third outer regions;forming a first contact opening through the insulative material to the elemental-form silicon of the first outer region in the vertical cross-section while the second and third outer regions are completely covered with masking material in the vertical cross-section; forming a second contact opening through the insulative material to the metal material of the second outer region in the vertical cross-section and a third contact opening through the insulative material to the elemental-form silicon of the third outer region in the vertical cross-section while the elemental-form silicon of the first outer region is completely covered with masking material in the vertical cross-section; within the third contact opening and while the second contact opening is outwardly exposed, etching through the elemental-form silicon of the third outer region to the metal material of the third outer region selectively relative to the metal material of the second outer region;
the elemental-form silicon of the first outer region being completely covered with masking material in the vertical cross-section during said etching; andafter said etching, forming conductive material in the first, second, and third contact openings. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method used in forming integrated circuitry comprising DRAM, comprising:
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providing a substrate comprising an array region comprising memory cells individually comprising an array transistor having a pair of source/drain regions and a gate comprising a wordline, a capacitor electrically coupled to one of the source/drain regions, and the other of the source/drain regions electrically coupled to a digitline;
the wordline comprising conductively-doped polysilicon directly above and directly against metal material;providing a peripheral-circuitry region adjacent the array region, the peripheral-circuitry region comprising a peripheral transistor, the wordline and the digitline extending from the array region into the peripheral-circuitry region, insulative material being directly above the wordline, the digitline, and the peripheral transistor in the peripheral-circuitry region; forming a first contact opening through the insulative material in the peripheral-circuitry region to elemental-form silicon of a source/drain region of the peripheral transistor in a vertical cross-section while the wordline and the digitline are completely covered with masking material in the peripheral-circuitry region in the vertical cross-section; in a single masking step, forming a second contact opening through the insulative material in the peripheral-circuitry region to conductive material of the digitline in the vertical cross-section and a third contact opening through the insulative material in the peripheral-circuitry region to the conductively-doped polysilicon of the wordline in the vertical cross-section while the elemental-form silicon of the source/drain region of the peripheral transistor is completely covered with masking material in the peripheral-circuitry region in the vertical cross-section; within the third contact opening and while the second contact opening is outwardly exposed, etching through the conductively-doped polysilicon to the wordline-metal material selectively relative to the conductive material of the digitline;
the elemental-form silicon of the source/drain region of the peripheral transistor being completely covered with masking material in the vertical cross-section during said etching; andafter said etching, forming conductive material in the first, second, and third contact openings. - View Dependent Claims (20, 21, 22, 23)
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Specification
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Current AssigneeMicron Technology, Inc.
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Original AssigneeMicron Technology, Inc.
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InventorsLee, Si-Woo
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Primary Examiner(s)Jahan, Bilkis
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Application NumberUS15/977,622Publication NumberTime in Patent Office648 DaysField of SearchNoneUS Class CurrentCPC Class CodesH01L 21/76802 by forming openings in diel...H01L 21/76816 Aspects relating to the lay...H01L 21/76877 Filling of holes, grooves o...H01L 23/5226 Via connections in a multil...H10B 12/488 Word linesH10B 12/50 Peripheral circuit region s...
