Three-dimensional vertical memory

• US 10,566,388 B2
• Filed: 09/20/2018
• Issued: 02/18/2020
• Est. Priority Date: 05/27/2018
• Status: Active Grant

• Current Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Bernstein, Allison
• Application Number:
  US16/137,512
• Publication Number:
  US 20190363132A1
• Time in Patent Office: 516 Days
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/841 Electrodes

Abstract

In a shared three-dimensional vertical memory (3D-M_V), each horizontal address line comprises at least two regions: a lightly-doped region and a low-resistivity region. The lightly-doped region is formed around selected memory holes and shared by a plurality of low-leakage memory cells. The low-resistivity region forms a conductive network to reduce the resistance of the horizontal address line.

Claims

1. A three-dimensional vertical memory (3D-M_V), comprising:

a semiconductor substrate including a substrate circuit;

a plurality of horizontal address lines above said substrate circuit;

a plurality of memory holes penetrating through said horizontal address lines;

a plurality of programmable layers covering the sidewalls of said memory holes;

a plurality of vertical address lines formed in said memory holes;

each of said horizontal address lines including at least a first region and a second region outside said first region, wherein said first region comprises at least a lightly-doped semiconductor material in contact with and surrounding at least one of said programmable layers in at least one of said memory holes, and said first region has a higher resistivity than said second region.

2. The 3D-M_V according to claim 1, wherein said lightly-doped semiconductor material in said first region is in contact with and surrounding selected ones of said programmable layers in at least three adjacent ones of said memory holes.

3. The 3D-M_V according to claim 2, wherein the intersections of said three adjacent ones of said memory holes and said each of said horizontal address lines are neither disposed on a single straight line nor separated by said second region.

4. The 3D-M_V according to claim 1, wherein the total area of said first region is larger than said second region.

5. The 3D-M_V according to claim 1, wherein a plurality of memory cells formed at the intersections of said each of said horizontal address lines and said vertical address lines, with the areal density of said memory cells in said first region larger than said second region.

6. The 3D-M_V according to claim 1, wherein:

said second region comprises at least a heavily-doped semiconductor material; and

,

said vertical address lines comprise at least a metallic material or another heavily-doped semiconductor material with polarity opposite to said heavily-doped semiconductor material.

7. The 3D-M_V according to claim 1, wherein:

said second region comprises at least a metallic material; and

,

said vertical address lines comprise at least a heavily-doped semiconductor material.

8. The 3D-M_V according to claim 1, wherein said programmable layer is one-time programmable, multiple-time programmable, or re-programmable.

9. A three-dimensional vertical memory (3D-M_V), comprising:

a semiconductor substrate including a substrate circuit;

a plurality of horizontal address lines stacked above said substrate circuit;

a plurality of memory holes penetrating through said horizontal address lines;

a plurality of programmable layers covering the sidewalls of said memory holes;

a plurality of vertical address lines formed in said memory holes;

each of said horizontal address lines including at least a first region and a second region outside said first region, wherein said first region comprises at least a lightly-doped semiconductor material surrounding at least three adjacent ones of said vertical address lines, and said first region has a higher resistivity than said second region.

10. The 3D-M_V according to claim 9, wherein the intersections of said three adjacent ones of said vertical address lines and said each of said horizontal address lines are neither disposed on a single straight line nor separated by said second region.

11. The 3D-M_V according to claim 9, wherein the total area of said first region is larger than said second region.

12. The 3D-M_V according to claim 9, wherein a plurality of memory cells formed at the intersections of said horizontal address lines and said vertical address lines, with the areal density of said memory cells in said first region larger than said second region.

13. The 3D-M_V according to claim 9, wherein:

said second region comprises at least a heavily-doped semiconductor material; and

,

said vertical address lines comprise at least a metallic material or another heavily-doped semiconductor material with polarity opposite to said heavily-doped semiconductor material.

14. The 3D-M_V according to claim 9, wherein:

said second region comprises at least a metallic material; and

,

said vertical address lines comprise at least a heavily-doped semiconductor material.

15. The 3D-M_V according to claim 9, wherein said programmable layer is one-time programmable, multiple-time programmable, or re-programmable.

16. A semiconductor memory, comprising:

a plurality of first-state memory cells including at least a first-state memory cell;

a plurality of second-state memory cells including at least a low-leakage memory cell and at least a high-leakage memory cell;

an address line coupling said first-state memory cell, said low-leakage memory cell and said high-leakage memory cell;

wherein said high-leakage memory cell has a smaller resistance than said low-leakage memory cell; and

, said low-leakage memory cell has a smaller resistance than said first-state memory cell.

17. The semiconductor memory according to claim 16, further comprising:

a semiconductor substrate including a substrate circuit;

a plurality of horizontal address lines stacked above said substrate circuit;

a plurality of memory holes penetrating through said horizontal address lines;

a plurality of programmable layers covering the sidewalls of said memory holes;

a plurality of vertical address lines formed in said memory holes;

wherein each of said horizontal address lines comprises at least first and second regions, with said first region having a higher resistivity than said second region;

wherein said low-leakage memory cell is formed at an intersection of said first region and a selected one of said vertical address lines; and

, said high-leakage memory cell is formed at another intersection of said second region and another selected one of said vertical address lines.

18. The semiconductor memory according to claim 16, wherein said first region comprises at least a lightly-doped semiconductor material;

and, said second region comprises at least a heavily-doped semiconductor material or a metallic material.

19. The semiconductor memory according to claim 16, wherein the total area of said first region is larger than said second region.

20. The semiconductor memory according to claim 16, wherein said semiconductor memory is one-time programmable, multiple-time programmable, or re-programmable.