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Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates

  • US 10,566,445 B2
  • Filed: 04/03/2018
  • Issued: 02/18/2020
  • Est. Priority Date: 04/03/2018
  • Status: Active Grant
First Claim
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1. A method of fabricating a semiconductor device, the method comprising:

  • performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include;

    forming gate spacers along a gate region of the nanosheet FET device;

    wherein each of the gate spacers comprises an upper segment and a lower segment;

    wherein forming the gate spacers comprises;

    forming dummy gate spacers along the gate region of the nanosheet FET device;

    using the dummy gates spacers as masks to remove portions of channel nanosheets of the nanosheet FET device; and

    replacing the dummy gate spacers with the gate spacers;

    wherein replacing the dummy gate spacers with the gate spacers comprises;

    forming a layer of the first type of material along the gate region of the nanosheet FET device; and

    replacing an upper region of the layer of the first type of material with a layer of the second type of material;

    wherein the layer of the second type of material comprises the upper segment of the gate spacer; and

    wherein replacing the dummy gate spacers with the gate spacers further comprises forming the lower segment of the gate spacer by using the upper segment of the gate spacer as a mask for removing portions of a lower region of the layer of the first type of material.

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