Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates

• US 10,566,445 B2
• Filed: 04/03/2018
• Issued: 02/18/2020
• Est. Priority Date: 04/03/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bi, Zhenxing, Cheng, Kangguo, Loubet, Nicolas J., Miao, Xin, Xu, Wenyu, Zhang, Chen
• Primary Examiner(s): Harriston, William A
• Application Number:
  US15/944,322
• Publication Number:
  US 20190305106A1
• Time in Patent Office: 686 Days
• Field of Search: None
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Embodiments of the invention are directed to method of fabricating a semiconductor device. A non-limiting embodiment of the method includes performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include forming gate spacers along a gate region of the nanosheet FET device, wherein each of the gate spacers comprises an upper segment and a lower segment.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include;

forming gate spacers along a gate region of the nanosheet FET device;

wherein each of the gate spacers comprises an upper segment and a lower segment;

wherein forming the gate spacers comprises;

forming dummy gate spacers along the gate region of the nanosheet FET device;

using the dummy gates spacers as masks to remove portions of channel nanosheets of the nanosheet FET device; and

replacing the dummy gate spacers with the gate spacers;

wherein replacing the dummy gate spacers with the gate spacers comprises;

forming a layer of the first type of material along the gate region of the nanosheet FET device; and

replacing an upper region of the layer of the first type of material with a layer of the second type of material;

wherein the layer of the second type of material comprises the upper segment of the gate spacer; and

wherein replacing the dummy gate spacers with the gate spacers further comprises forming the lower segment of the gate spacer by using the upper segment of the gate spacer as a mask for removing portions of a lower region of the layer of the first type of material.

2. The method of claim 1, wherein:

the upper segment comprises a second type of material; and

the lower segment comprises a first type of material.

3. The method of claim 1, wherein the first type of material comprises a first type of low-k material.

4. The method of claim 3, wherein the second type of material comprises a second type of low-k material.

5. The method of claim 2, wherein the fabrication operations further comprise forming inner spacers between channel nano sheets of the nanosheet FET device.

6. The method of claim 5, wherein inner spacers comprise the first type of material.

7. The method of claim 6, wherein the first type of material comprises a first type of low-k material.

8. The method of claim 7, wherein the second type of material comprises a second type of low-k material.

9. A method of fabricating a semiconductor device, the method comprising:

performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include;

forming gate spacers along a gate region of the nanosheet FET device; and

forming inner spacers between channel nanosheets of the nanosheet FET device;

wherein each of the gate spacers comprises an upper segment and a lower segment;

wherein the upper segment comprises a second type of material;

wherein the lower segment comprises a first type of material;

wherein inner spacers comprise the first type of material;

wherein forming the gate spacers comprises;

forming dummy gate spacers along the gate region of the nanosheet FET device;

using the dummy gates spacers as masks to remove portions of channel nanosheets of the nanosheet FET device; and

replacing the dummy gate spacers with the gate spacers;

wherein replacing the dummy gate spacers with the gate spacers comprises;

forming a layer of the first type of material along the gate region of the nanosheet FET device; and

replacing an upper region of the layer of the first type of material with a layer of the second type of material;

wherein the layer of the second type of material comprises the upper segment of the gate spacer; and

wherein replacing the dummy gate spacers with the gate spacers further comprises forming the lower segment of the gate spacer by using the upper segment of the gate spacer as a mask for removing portions of a lower region of the layer of the first type of material.

10. The method of claim 9, wherein:

the first type of material comprises a first type of low-k material; and

the second type of material comprises a second type of low-k material.