Array substrate and method for manufacturing the same

• US 10,566,458 B2
• Filed: 09/01/2015
• Issued: 02/18/2020
• Est. Priority Date: 08/10/2015
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Liu, Yang
• Primary Examiner(s): Loke, Steven H
• Assistant Examiner(s): Rhodes, Juanita B
• Application Number:
  US14/897,677
• Publication Number:
  US 20180158953A1
• Time in Patent Office: 1,631 Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Disclosed are an array substrate and a method for manufacturing the same, which belong to the technical field of display, and are able to solve the technical problem that the existing process for manufacturing array substrates is too complex. The array substrate includes a plurality of sub-pixel units formed on a base substrate. Each of the sub-pixel units comprises a thin film transistor and a second pixel electrode. An active layer of the thin film transistor is made of an oxide semiconductor. The second pixel electrode is made of a plasma treated transparent oxide semiconductor. The array substrate provided by the present disclosure can be used in an IPS or FFS liquid crystal display device.

Claims

1. A method for manufacturing an array substrate, comprising steps of:

forming a scan line, a common electrode line, a gate of a thin film transistor, and a first pixel electrode on a base substrate;

forming a gate insulating layer;

forming an oxide semiconductor pattern, a data line, and a source of the thin film transistor on the gate insulating layer, wherein the oxide semiconductor pattern comprises an active layer of the thin film transistor, and a second pixel electrode pattern;

forming a passivation layer;

etching the passivation layer, so as to expose the second pixel electrode pattern of the oxide semiconductor pattern and allow the source and the active layer of the thin film transistor to remain covered by the passivation layer; and

performing plasma treatment on the second pixel electrode pattern of the oxide semiconductor pattern after the forming and etching the passivation layer, so as to form a second pixel electrode, wherein the source and the active layer of the thin film transistor are masked by the passivation layer and protected from the plasma treatment.

2. The method according to claim 1, wherein the step of performing plasma treatment on the second pixel electrode pattern of the oxide semiconductor pattern specifically comprises:

performing plasma treatment on the second pixel electrode pattern of the oxide semiconductor pattern with SF₆, N₂, Ar or He.

3. The method according to claim 1, wherein the step of forming the scan line, the common electrode line, the gate of the thin film transistor, and the first pixel electrode on the base substrate, specifically comprises sub steps of:

forming a transparent electrode layer and a first metal layer in sequence on the base substrate;

coating the first metal layer with a photoresist, exposing and developing the photoresist with a half-tone mask, a gray-tone mask, or a single-slit mask;

etching the first metal layer and the transparent electrode layer, so as to form the scan line, the common electrode line, and the gate of the thin film transistor;

ashing the photoresist;

etching the first metal layer, so as to form the first pixel electrode; and

removing residual photoresist.

4. The method according to claim 1, wherein the step of forming the oxide semiconductor pattern, the data line, and the source of the thin film transistor on the gate insulating layer, specifically comprises sub steps of:

forming an oxide semiconductor layer and a second metal layer in sequence on the gate insulating layer;

coating the second metal layer with a photoresist, exposing and developing the photoresist a with a half-tone mask, a gray-tone mask, or a single-slit mask;

etching the second metal layer and the oxide semiconductor layer, so as to form the data line and the source of the thin film transistor;

ashing the photoresist;

etching the second metal layer, so as to form the oxide semiconductor pattern; and

removing residual photoresist.

5. The method according to claim 1, wherein the step of etching the passivation layer, so as to expose the second pixel electrode pattern of the oxide semiconductor pattern, specifically comprises sub steps of:

coating the passivation layer with a photoresist, exposing and developing the photoresist with a mask;

etching the passivation layer, so as to expose the second pixel electrode pattern of the oxide semiconductor pattern; and

removing residual photoresist.

6. The method according to claim 5, wherein the step of etching the passivation layer specifically is:

etching the passivation layer with sulfur hexafluoride.

7. An array substrate, comprising:

a base substrate;

a scan line, a common electrode line, a gate of a thin film transistor, and a first pixel

electrode disposed on the base substrate;

a gate insulating layer that covers the scan line, the common electrode line, the gate of the

thin film transistor, the first pixel electrode, and the base substrate;

an oxide semiconductor pattern, a data line, and a source of the thin film transistor disposed

on the gate insulating layer, wherein the oxide semiconductor pattern comprises an active layer of

the thin film transistor and a second pixel electrode; and

a passivation layer that covers the active layer and the source of the thin film transistor and exposes the second pixel electrode,

wherein the active layer of the thin film transistor is located at a same layer as the second pixel electrode, the active layer of the thin film transistor being made of an oxide semiconductor, and the second pixel electrode being made of a plasma treated transparent oxide semiconductor.

8. The array substrate according to claim 7,

wherein the active layer of the thin film transistor is located above the gate.

9. The array substrate according to claim 7,

wherein the common electrode line and the scan line are both located at a same layer as the gate;

and

wherein the data line is located at a same layer as the source.