Termination structure for insulated gate semiconductor device and method

• US 10,566,466 B2
• Filed: 04/26/2019
• Issued: 02/18/2020
• Est. Priority Date: 06/27/2018
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Quddus, Mohammed Tanvir, Mudholkar, Mihir, Hossain, Zia
• Primary Examiner(s): Ward, Eric A.
• Application Number:
  US16/396,446
• Publication Number:
  US 20200006579A1
• Time in Patent Office: 298 Days
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

Claims

1. A semiconductor device structure, comprising:

a region of semiconductor material comprising;

a first conductivity type;

a first major surface;

a second major surface opposite to the first major surface;

an active region; and

a termination region;

an active structure disposed in the active region comprising;

a first active trench extending from the first major surface into the region of semiconductor material to a first depth; and

a first conductive structure within the first active trench and electrically isolated from the region of semiconductor material by a first dielectric structure, wherein the first active trench has a first width proximate to the first major surface;

a termination structure disposed in the termination region comprising;

a first termination trench extending from the first major surface into the region of semiconductor material to a second depth;

a second conductive structure within the first termination trench and electrically isolated from the region of semiconductor material by a second dielectric structure, wherein;

the first termination trench comprises;

a second width proximate to the first major surface;

a first side surface;

a second side surface opposite to the first side surface; and

a first lower surface extending between the first side surface and the second side surface;

the first side surface is interposed between the second side surface and the first active trench; and

the second conductive structure comprises;

a first conductive spacer disposed proximate to the first side surface of the first termination trench; and

a second conductive spacer disposed proximate to the second side surface of the first termination trench; and

a dielectric layer disposed overlying a portion of the first major surface and overlapping the first conductive spacer and overlapping the second conductive spacer;

a first doped region comprising a second conductivity type opposite the first conductive type in the region of semiconductor material adjacent to the first major surface and adjacent to the second side surface of the first termination trench;

a second doped region comprising the second conductivity type in the region of semiconductor material adjacent to the second side surface of the first termination trench;

a third doped region comprising the second conductivity type in the region of semiconductor material adjacent to the first lower surface of the first termination trench, wherein;

the first doped region and the second doped region overlap; and

the second doped region and the third doped region overlap;

a Schottky contact structure having a first portion disposed adjacent to the first major surface on opposing sides of the first active trench and a second portion disposed within the first doped region; and

a first conductive layer disposed overlying the first major surface and electrically coupled to the first portion and the second portion of Schottky contact structure.

2. The semiconductor device of claim 1, wherein:

the first conductive layer is electrically coupled to the first conductive spacer.

3. The semiconductor device of claim 1, wherein:

an opening is disposed within the dielectric layer proximate to the first lower surface of the first termination trench.

4. The semiconductor device of claim 3, wherein:

the first conductive layer is further electrically coupled to the region of semiconductor material in the opening.

5. The semiconductor device of claim 4, wherein:

a third portion of the Schottky contact structure is disposed within the third doped region adjacent the opening.

6. The semiconductor device of claim 1, further comprising:

a fourth doped region comprising the second conductivity type in the region of semiconductor material adjacent to the first side surface of the first termination trench, wherein the fourth doped region and the third doped region overlap.

7. The semiconductor device of claim 6, wherein:

the first conductive layer is electrically coupled to the fourth doped region proximate to the first side surface of the termination trench.

8. The semiconductor device of claim 6, wherein:

the second doped, the third doped region, and the fourth doped region comprises a continuous doped structure that separates the first termination trench from the region of semiconductor material.

9. The semiconductor device of claim 1, further comprising:

a fourth doped region comprising the second conductivity type in the region of semiconductor material adjacent to the first major surface, wherein;

the first doped region is interposed between the fourth doped region and the second side surface of the first termination trench; and

the fourth doped region is laterally spaced apart from the first doped region.

10. The semiconductor device of claim 9, wherein:

the fourth doped region comprises an electrically floating region.

11. The semiconductor device of claim 10, wherein:

the first conductive layer laterally overlaps the fourth doped region in a cross-sectional view.

12. The semiconductor device of claim 1, wherein;

the region of semiconductor material comprises a substrate and a semiconductor layer disposed overlying the substrate;

the semiconductor layer provides the first major surface; and

the semiconductor device further comprises;

a substrate contact structure extending from the first major surface into the substrate.

13. A semiconductor device structure, comprising:

a region of semiconductor material comprising;

a first conductivity type;

a first major surface;

a second major surface opposite to the first major surface;

an active region; and

a termination region;

an active structure disposed in the active region comprising;

a first active trench extending from the first major surface into the region of semiconductor material; and

a first conductive structure within the first active trench and electrically isolated from the region of semiconductor material by a first dielectric structure;

a termination structure disposed in the termination region comprising;

a first termination trench extending from the first major surface into the region of semiconductor material;

a second conductive structure within the first termination trench and electrically isolated from the region of semiconductor material by a second dielectric structure, wherein;

the first termination trench comprises;

a first side surface;

a second side surface opposite to the first side surface; and

a first lower surface extending between the first side surface and the second side surface;

the first side surface is interposed between the second side surface and the first active trench; and

the second conductive structure comprises a first conductive spacer disposed proximate to the first side surface of the first termination trench; and

a dielectric layer disposed overlying a portion of the first major surface and overlapping the first conductive spacer;

a first doped region comprising a second conductivity type opposite the first conductive type in the region of semiconductor material adjacent to the first lower surface of the first termination trench;

a Schottky contact structure having a first portion disposed adjacent to the first major surface on opposing sides of the first active trench; and

a first conductive layer disposed overlying the first major surface and electrically coupled to the first portion and the second portion of Schottky contact structure and electrically coupled to the first doped region.

14. The semiconductor device of claim 13, further comprising:

a second doped region comprising the second conductivity type in the region of semiconductor material adjacent to the lower surface of the first termination trench and laterally spaced apart from the first doped region.

15. The semiconductor device of claim 13, wherein:

the dielectric layer comprises an opening adjacent to the first doped region; and

the first conductive layer electrically coupled to the first doped region through the opening.

16. The semiconductor device of claim 15, wherein

the first conductive layer is electrically connected to the first conductive spacer.

17. The semiconductor device of claim 13, further comprising:

a second doped region comprising the second conductivity type in the region of semiconductor material adjacent to the first side surface of the first termination trench, wherein;

the second doped region overlaps the first doped region; and

the first conductive layer is electrically coupled to the second doped region proximate to the first side surface of the first termination trench.

18. The semiconductor device of claim 17, wherein:

the first doped region laterally extends the width of the first termination trench.

19. The semiconductor device of claim 13, wherein:

the region of semiconductor material comprises a substrate and a semiconductor layer disposed overlying the substrate;

the semiconductor layer provides the first major surface; and

the semiconductor device further comprises;

a substrate contact structure extending from the first major surface into the substrate.

20. A semiconductor device structure, comprising:

a region of semiconductor material comprising;

a first conductivity type;

a first major surface;

a second major surface opposite to the first major surface;

an active region; and

a termination region;

an active structure disposed in the active region comprising;

a first active trench extending from the first major surface into the region of semiconductor material; and

a first conductive structure within the first active trench and electrically isolated from the region of semiconductor material by a first dielectric structure;

a termination structure disposed in the termination region comprising;

a first termination trench extending from the first major surface into the region of semiconductor material;

a second conductive structure within the first termination trench and electrically isolated from the region of semiconductor material by a second dielectric structure, wherein;

the first termination trench comprises;

a first side surface;

a second side surface opposite to the first side surface; and

a first lower surface extending between the first side surface and the second side surface;

the first side surface is interposed between the second side surface and the first active trench; and

the second conductive structure comprises;

a first conductive spacer disposed proximate to the first side surface of the first termination trench; and

a second conductive spacer disposed proximate to the second side surface of the first termination trench; and

a dielectric layer disposed overlying a portion of the first major surface and overlapping the first conductive spacer and overlapping the second conductive spacer;

a first doped region comprising a second conductivity type opposite the first conductive type in the region of semiconductor material adjacent to a first lower corner of the first termination trench;

a second doped region comprising the second conductivity type in the region of semiconductor material adjacent to a second lower corner of the first termination trench;

a Schottky contact structure having a first portion disposed adjacent to the first major surface on opposing sides of the first active trench and a second portion disposed in a portion of the region of semiconductor material proximate to the lower surface of the first termination trench; and

a first conductive layer disposed overlying the first major surface and electrically coupled to the first portion and the second portion of Schottky contact structure.