Signal processing circuit

• US 10,566,984 B2
• Filed: 03/13/2019
• Issued: 02/18/2020
• Est. Priority Date: 05/11/2018
• Status: Active Grant

• Current Assignee: Omron Corporation
• Original Assignee: Omron Corporation
• Inventors: Kikunaga, Yoshitaka
• Primary Examiner(s): Jeanglaude, Jean B
• Application Number:
  US16/351,520
• Publication Number:
  US 20190348991A1
• Time in Patent Office: 342 Days
• Field of Search: 341155, 341162
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2203/45134 the whole differential amplifier together with other coupled stages being fully differential realised
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03H 11/0455 Multiple integrator loop feedback filters
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295

Abstract

A signal processing circuit with high noise resistance is realized. The signal processing circuit includes: a first pre-stage circuit that includes a first input terminal; and a second pre-stage circuit that includes a second input terminal. A resistive element with one end connected to the first input terminal and a capacitative element with one electrode connected to the ground are provided in the first pre-stage circuit. The other end of the first resistive element and the other electrode of the first capacitative element are connected to each other. An output node of the first pre-stage circuit and an output node of the second pre-stage circuit are connected to a post-stage circuit.

Claims

1. A signal processing circuit comprising:

a first pre-stage circuit that includes a first input terminal for receiving one of differential input;

a second pre-stage circuit that includes a second input terminal for receiving another one of the differential input;

a post-stage circuit that includes a differential output amplifier; and

an analog-to-digital conversion circuit connected to the post-stage circuit,

wherein the first pre-stage circuit includes a first resistive element with one end connected to the first input terminal and a first capacitative element with one grounded electrode,

an other end of the first resistive element and an other electrode of the first capacitative element are connected to each other, and

an output node of the first pre-stage circuit and an output node of the second pre-stage circuit are connected to the post-stage circuit.

2. The signal processing circuit according to claim 1, wherein

the post-stage circuit includes a second resistive element with one end connected to a negative output terminal of the differential output amplifier and a second capacitative element with one grounded electrode, and

an other end of the second resistive element, an other electrode of the second capacitative element, and one of two input terminals of the analog-to-digital conversion circuit are connected to each other.

3. The signal processing circuit according to claim 1, wherein circuit configurations of the first pre-stage circuit and the second pre-stage circuit are the same.

4. The signal processing circuit according to claim 2, wherein circuit configurations of the first pre-stage circuit and the second pre-stage circuit are the same.

5. The signal processing circuit according to claim 2, wherein

the second pre-stage circuit includes a third resistive element with one end connected to the second input terminal and a third capacitative element with one grounded electrode, and

an other end of the third resistive element and an other electrode of the third capacitative element are connected to each other.

6. The signal processing circuit according to claim 5, wherein

the post-stage circuit includes a fourth resistive element with one end connected to a positive output terminal of the differential output amplifier and a fourth capacitative element with one grounded electrode, and

an other end of the fourth resistive element, an other electrode of the fourth capacitative element, and the other of the two input terminals of the analog-to-digital conversion circuit are connected to each other.

7. The signal processing circuit according to claim 6, wherein the negative output terminal and a positive input terminal of the differential output amplifier are connected via a fifth resistive element, and the positive output terminal and a negative input terminal of the differential output amplifier are connected via a sixth resistive element.

8. The signal processing circuit according to claim 7, wherein resistance values of the first resistive element and the third resistive element are the same, resistance values of the second resistive element and the fourth resistive element are the same, capacitance values of the first capacitative element and the third capacitative element are the same, and capacitance values of the second capacitative element and the fourth capacitative element are the same.

9. The signal processing circuit according to claim 7, wherein the output node of the first pre-stage circuit is connected to the positive input terminal of the differential output amplifier via a seventh resistive element, and the output node of the second pre-stage circuit is connected to the negative input terminal of the differential output amplifier via an eighth resistive element.

10. The signal processing circuit according to claim 7, wherein the first pre-stage circuit and the second pre-stage circuit are connected to each other via a fifth capacitative element.

11. The signal processing circuit according to claim 1, wherein analog signals from an external device are supplied to the first input terminal and the second input terminal.

12. The signal processing circuit according to claim 2, wherein analog signals from an external device are supplied to the first input terminal and the second input terminal.

13. The signal processing circuit according to claim 3, wherein analog signals from an external device are supplied to the first input terminal and the second input terminal.

14. The signal processing circuit according to claim 5, wherein analog signals from an external device are supplied to the first input terminal and the second input terminal.

15. The signal processing circuit according to claim 6, wherein analog signals from an external device are supplied to the first input terminal and the second input terminal.

16. The signal processing circuit according to claim 7, wherein analog signals from an external device are supplied to the first input terminal and the second input terminal.

17. The signal processing circuit according to claim 8, wherein analog signals from an external device are supplied to the first input terminal and the second input terminal.

18. The signal processing circuit according to claim 9, wherein analog signals from an external device are supplied to the first input terminal and the second input terminal.

19. The signal processing circuit according to claim 10, wherein analog signals from an external device are supplied to the first input terminal and the second input terminal.