Performing system functional test on a chip having partial-good portions

• US 10,571,519 B2
• Filed: 03/08/2016
• Issued: 02/25/2020
• Est. Priority Date: 03/08/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Agrawal, Mitesh A., Lobo, Preetham M., Motika, Franco, Parker, John D., Salem, Gerard M.
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US15/063,666
• Publication Number:
  US 20170261551A1
• Time in Patent Office: 1,449 Days
• Field of Search: 714726, 714728, 714731, 714736
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/3181 Functional testing G01R31/3177 takes precedence

Abstract

Embodiments include methods, and computer system, and computer program products for performing system functional test on a chip having partial-good portions. Aspects include: initializing, by system functional test software, a service engine of the chip, performing, by service engine, system functional test, and completing system functional test of chip. The chip may include service engine, a service engine memory and one or more “partial-good” portions. The initializing may include: loading system functional test software into the service engine memory, identifying each “partial-good” portion of the chip, writing a “partial-good” parameter for each “partial-good” portion of the chip identified to service engine memory, and triggering execution of system functional test. Method may include: decoding system functional test software, retrieving “partial-good” parameters, initializing “partial-good” portions of chip, and performing system functional test on “partial-good” portions of chip. The chip may include is a processor chip that has one or more “partial-good” cores.

Claims

1. A method for performing system functional test on a chip having partial-good portions comprising:

initializing, by system functional test software, a service engine of the chip undergoing a system functional test, wherein the initializing includes;

loading the system functional test software into a service engine memory of the chip;

identifying each “

partial-good”

portion of the chip;

writing a “

partial-good”

parameter for each “

partial-good”

portion of the chip identified to a first predetermined location of the service engine memory;

triggering execution of the system functional test;

performing, by the service engine, the system functional test, wherein the performing includes; and

decoding the system functional test software;

retrieving the “

partial-good”

parameters from the first predetermined location of the service engine memory;

initializing the “

partial-good”

portions of the chip according to “

partial-good”

parameter; and

performing the system functional test on the “

partial-good”

portions of the chip without performing the system functional test in all defective portions of the chip; and

completing the system functional test of the chip.

2. The method of claim 1, wherein the chip comprises one or more “

partial-good”

portions, and each of the one or more “

partial-good”

portions is identified by a “

partial-good”

parameter.

3. The method of claim 1, wherein the completing comprises:

writing results of the system functional test to a second predetermined location of the service engine memory.

4. The method of claim 1, wherein the chip comprises a processor chip, and the processor chip comprises one or more “

partial-good”

cores.

5. A computer system for performing system functional test on a chip having partial-good portions comprising a processor and a memory storing system functional test software for the computer system which, when executed at the processor of the computer system, are configured to perform:

initializing a service engine of the chip undergoing system functional test, wherein the chip comprises one or more “

partial-good”

portions, and each of the one or more “

partial-good”

portions is identified by a “

partial-good”

parameter, and wherein the initializing includes;

loading the system functional test software into the service engine memory;

identifying each “

partial-good”

portion of the chip;

writing a “

partial-good”

parameter for each “

partial-good”

portion of the chip identified to a first predetermined location of the service engine memory;

triggering execution of the system functional test;

performing, by the service engine, the system functional test, wherein the performing includes;

decoding the system functional test software;

retrieving the “

partial-good”

parameters from the first predetermined location of the service engine memory;

initializing the “

partial-good”

portions of the chip according to “

partial-good”

parameter; and

performing system functional test on the “

partial-good”

portions of the chip without performing the system functional test in all defective portions of the chip; and

completing the system functional test of the chip.

6. The computer system of claim 5, wherein the chip comprises the service engine, and a service engine memory.

7. The computer system of claim 6, wherein the completing comprises:

writing results of the system functional test to a second predetermined location of the service engine memory.

8. The computer system of claim 5, wherein the chip comprises a processor chip, and the processor chip comprises the one or more “

partial-good”

cores.

9. A computer program product operable on a computer system for performing system functional test on a chip having partial-good portions, comprising a non-transitory computer storage medium readable by the computer system having a processor and a memory configured to store system functional test software for execution by the processor of the computer system for performing a method comprising:

initializing a service engine of the chip undergoing system functional test, wherein the chip comprises one or more “

partial-good”

portions, and each of the one or more “

partial-good”

portions is identified by a “

partial-good”

parameter, and wherein the initializing includes;

loading the system functional test software into the service engine memory;

identifying each “

partial-good”

portion of the chip;

writing a “

partial-good”

parameter for each “

partial-good”

portion of the chip identified to a first predetermined location of the service engine memory;

triggering execution of the system functional test;

performing, by the service engine, the system functional test, wherein the performing includes;

decoding the system functional test software;

retrieving the “

partial-good”

parameters from the first predetermined location of the service engine memory;

initializing the “

partial-good”

portions of the chip according to “

partial-good”

parameter; and

performing system functional test on the “

partial-good”

portions of the chip without performing the system functional test in all defective portions of the chip; and

completing the system functional test of the chip.

10. The computer program product of claim 9, wherein the completing comprises:

writing results of the system functional test to a second predetermined location of the service engine memory.

11. The computer program product of claim 9, wherein the chip comprises a processor chip, and the processor chip comprises the one or more “

partial-good”

cores.