Managed NVM adaptive cache management

• US 10,572,388 B2
• Filed: 08/30/2017
• Issued: 02/25/2020
• Est. Priority Date: 08/30/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Christensen, Carla L., Huang, Jianmin, Jean, Sebastien Andre, Tanpairoj, Kulachet
• Primary Examiner(s): Knight, Paul M
• Application Number:
  US15/691,147
• Publication Number:
  US 20190065388A1
• Time in Patent Office: 909 Days
• Field of Search: None
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3212 Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

Claims

1. A memory device, comprising:

an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, memory cells in the array that are configured as SLC comprising an SLC cache;

a controller, the controller executing firmware instructions, which cause the controller to perform operations comprising;

receiving an incoming large data transfer indication prior to receiving the data corresponding to the incoming large data transfer;

responsive to receiving the incoming large data transfer indication, reconfiguring a first set of one or more memory cells of the array that are configured as MLC to SLC, a size of the set determined based upon a logical block address utilization and an expected size of the large data transfer;

receiving the data corresponding to the incoming large data transfer and writing at least a portion of the data to the SLC cache;

receiving an ambient temperature indication; and

responsive to the ambient temperature indication, bypassing the SLC cache when servicing a subsequent write request.

2. The memory device of claim 1, wherein the operations of receiving the indication comprises receiving the indication from a host over a communications interface.

3. The memory device of claim 2, wherein the communication interface is an interface according to a Universal Flash Storage (UFS) device.

4. The memory device of claim 1, wherein the operations further comprise:

receiving an indication from a host that a battery level measured by the host is below a predetermined threshold;

responsive to receiving the indication from the host, placing data of a first write request in memory cells of the array configured as MLC and not writing the data in memory cells of the array configured as the SLC cache;

subsequent to receiving the indication from the host, receiving a second indication from the host, the second indication indicating that the battery level is above the predetermined threshold and in response, placing second data of a second request in the SLC cache; and

subsequent to placing the data of the second request in the SLC cache, moving the second data of the second request to memory cells of the array configured as MLC.

5. The memory device of claim 4, wherein the operations further comprise delaying a reconfiguration of a MLC memory cell to an SLC memory cell responsive to the indication from the host that the battery level measured by the host is below the predetermined threshold.

6. The memory device of claim 4, wherein the host is associated with an operating system, and wherein the battery is a battery of a mobile computing device.

7. A memory device, comprising:

an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, memory cells in the array that are configured as SLC comprising an SLC cache;

a controller, the controller executing firmware instructions, which cause the controller to perform operations comprising;

receiving an incoming large data transfer indication prior o receiving the data corresponding to the incoming large data transfer;

responsive to receiving the incoming large data transfer indication, reconfiguring a first set of one or more memory cells of the array that are configured as MLC to SLC, a size of the set determined based upon a logical block address utilization and an expected size of the large data transfer;

receiving the data corresponding to the incoming large data transfer and writing the data to the SLC cache;

receiving an ambient temperature indication; and

responsive to the ambient temperature indication, bypassing the SLC cache when servicing a subsequent write request.

8. The memory device of claim 7, wherein the operations further comprise receiving a low power indication, and in response, bypassing an SLC cache when servicing a subsequent write request.

9. The memory device of claim 7, wherein the large data transfer indication is provided by an operating system.

10. The memory device of claim 7, wherein the operations comprise receiving a sleep or hibernate indication, and in response, executing an SLC cache routine to begin garbage collection.

11. A non-transitory machine-readable medium, comprising instructions, that when performed by a machine, causes the machine to perform operations comprising:

at a memory device including an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, memory cells in the array that are configured as SLC comprising an SLC cache;

receiving an incoming large data transfer indication prior to receiving the data corresponding to the incoming large data transfer;

responsive to receiving the incoming large data transfer indication, reconfiguring a first set of one or more memory cells of the array that are configured as MLC to SLC, a size of the set determined based upon a logical block address utilization and an expected size of the large data transfer;

receiving the data corresponding to the incoming large data transfer and writing the data to the SLC cache;

receiving an ambient temperature indication; and

responsive to the ambient temperature indication, bypassing the SLC cache when servicing a subsequent write request.

12. The non-transitory machine-readable medium of claim 11, wherein the operations further comprise receiving a low power indication, and in response, bypassing an SLC cache when servicing a subsequent write request.

13. The non-transitory machine-readable medium of claim 11, wherein the large data transfer indication is provided by an operating system.

14. The non-transitory machine-readable medium of claim 11, wherein the operations comprise receiving a sleep or hibernate indication, and in response, executing an SLC cache routine to begin garbage collection.