Placement and routing of cells using cell-level layout-dependent stress effects
First Claim
1. A method of improving the operation of a place-and-route system in the selection of a target cell in a target circuit design layout for fabrication of an integrated circuit, comprising:
- providing to a computer system a cell library describing a plurality of cells;
for placement into a target position in the target circuit design layout, a computer system selecting a target cell from the cell library in dependence upon a circuit design, the target position having one or more neighboring cells in the target circuit design layout; and
placing the target cell into the target position in the target circuit design layout,wherein the cell library further indicates, for each cell in the cell library;
boundary conditions imposed by the cell on neighboring cells in a layout, anddependency of performance of the cell on boundary conditions imposed on the cell by neighboring cells in a layout;
and wherein a computer system selecting the target cell from the cell library comprises;
a computer system determining from the cell library, boundary conditions imposed on the target position by each of a plurality of cells neighboring the target position in the target circuit design layout; and
a computer system selecting the target cell further in dependence upon the determined boundary conditions and the dependency, as indicated in the cell library, of performance of the target cell on boundary conditions imposed on the target cell by neighboring cells in a layout.
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Accused Products
Abstract
Disclosed is technology for placing cells in a circuit design layout to thereby improve the operation of place- and route equipment used for fabrication of an integrated circuit. The target cells are chosen from a cell library which includes descriptions for a plurality of cells, and information about dependency of each cell on hypothetical boundary conditions that can be imposed on the cell by any stress source originating in the vicinity of said cell in the layout. In order to select a cell for a target location in the layout, boundary conditions imposed on the target position by each of the cells neighboring the target position are determined. The system then selects an appropriate target cell in dependence upon the determined boundary conditions and the performance of the cell based on the boundary conditions imposed on the cell by the neighboring cells from the cell library.
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Citations
34 Claims
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1. A method of improving the operation of a place-and-route system in the selection of a target cell in a target circuit design layout for fabrication of an integrated circuit, comprising:
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providing to a computer system a cell library describing a plurality of cells; for placement into a target position in the target circuit design layout, a computer system selecting a target cell from the cell library in dependence upon a circuit design, the target position having one or more neighboring cells in the target circuit design layout; and placing the target cell into the target position in the target circuit design layout, wherein the cell library further indicates, for each cell in the cell library; boundary conditions imposed by the cell on neighboring cells in a layout, and dependency of performance of the cell on boundary conditions imposed on the cell by neighboring cells in a layout; and wherein a computer system selecting the target cell from the cell library comprises; a computer system determining from the cell library, boundary conditions imposed on the target position by each of a plurality of cells neighboring the target position in the target circuit design layout; and a computer system selecting the target cell further in dependence upon the determined boundary conditions and the dependency, as indicated in the cell library, of performance of the target cell on boundary conditions imposed on the target cell by neighboring cells in a layout. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A system for improving the operation of a place-and-route equipment in the selection of a target cell in a target circuit design layout for fabrication of an integrated circuit, the system comprising a memory and a data processor coupled to the memory, the data processor configured to:
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provide to a computer system a cell library describing a plurality of cells; for placement into a target position in the target circuit design layout, select a target cell from the cell library in dependence upon a circuit design, the target position having one or more neighboring cells in the target circuit design layout; and place the target cell into the target position in the target circuit design layout, wherein the cell library further indicates, for each cell in the cell library; boundary conditions imposed by the cell on neighboring cells in a layout, and dependency of performance of the cell on boundary conditions imposed on the cell by neighboring cells in a layout; and wherein in selecting the target cell from the cell library the data processor is configured to; determine from the cell library, boundary conditions imposed on the target position by each of a plurality of cells neighboring the target position in the target circuit design layout; and select the target cell further in dependence upon the determined boundary conditions and the dependency, as indicated in the cell library, of performance of the target cell on boundary conditions imposed on the target cell by neighboring cells in a layout. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A non-transitory computer readable medium, for use with a cell library describing a plurality of cells, which indicates, for each cell in the cell library:
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boundary conditions imposed by the cell on neighboring cells in a layout; and dependency of performance of the cell on boundary conditions imposed on the cell by neighboring cells in a layout, the computer readable medium having stored thereon a plurality of instructions which when executed by a processor cause the processor to; select, for placement into a target position in the target circuit design layout, a target cell from the cell library in dependence upon a circuit design, the target position having one or more neighboring cells in the target circuit design layout; and place the target cell into the target position in the target circuit design layout, wherein in selecting the target cell from the cell library the processor; determines from the cell library, boundary conditions imposed on the target position by each of a plurality of cells neighboring the target position in the target circuit design layout; and selects the target cell further in dependence upon the determined boundary conditions and the dependency, as indicated in the cell library, of performance of the target cell on boundary conditions imposed on the target cell by neighboring cells in a layout. - View Dependent Claims (32, 33, 34)
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Specification