Method of etch model calibration using optical scatterometry

• US 10,572,697 B2
• Filed: 04/06/2018
• Issued: 02/25/2020
• Est. Priority Date: 04/06/2018
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Feng, Ye, Musselman, Marcus, Bailey, III, Andrew D., Tetiker, Mehmet Derya, Sriraman, Saravanapriyan, Zhang, Yan, Mailfert, Julien
• Primary Examiner(s): Aisaka, Bryce M
• Application Number:
  US15/946,940
• Publication Number:
  US 20190311083A1
• Time in Patent Office: 690 Days
• Field of Search: 716 54
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 1/78 by charged particle beam [CPB], e.g. electron beam patterning of masks
• CPC Class Codes: G03F 1/80 Etching
• CPC Class Codes: G03F 1/86 by charged particle beam [CPB]
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70516 Calibration of components of the microlithographic apparatus, e.g. light sources, addressable masks or detectors
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G06F 30/23 using finite element methods [FEM] or finite difference methods [FDM]
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

Claims

1. A computer-implemented method of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation from process parameter values characterizing the semiconductor device fabrication operation, the method comprising:

(a) receiving current values of one or more floated process model parameters to be optimized, wherein the one or more floated process model parameters comprise a reaction rate constant, a reactant and/or product sticking coefficient, a reactant diffusion constant, a product diffusion constant, an optical dispersion property, a vertical etch rate, a lateral etch rate, a nominal etch depth, an etch selectivity, a tilt angle of ion entry, a twist angle of ion entry, a visibility into a feature, an angular distribution, a sputter maximum yield angle, an etch ratio per crystal direction, or a combination of these;

(b) producing a configured process simulation model by providing to the process simulation model the current values of the one or more floated process model parameters and a set of fixed process model parameter value(s);

(c) generating, using the configured process simulation model, a computationally predicted result of the semiconductor device fabrication operation;

(d) comparing the computationally predicted result of the semiconductor device fabrication operation with a metrology result obtained from one or more substrate features produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under the set of fixed process parameter values, wherein the comparing produces one or more cost values based on a difference between the computationally predicted result of the semiconductor device fabrication operation and the metrology result;

(e) using the one or more cost values and/or a convergence check to generate an update of the current values of the one or more floated process model parameters;

(f) performing operation (b) with the update of the current values of the one or more floated process model parameters; and

(g) repeating (c)-(f) until the current values of the one or more floated process model parameters converge to produce final values of the one or more floated process model parameters that minimize the cost values.

2. The method of claim 1, wherein the set of fixed process model parameter value(s) or the one or more floated process model parameters include one or more values of temperature in the reaction chamber, one or more RF conditions in the reaction chamber, one or more process gases in in the reaction chamber, a pressure in the reaction chamber, or any combination thereof.

3. The method of claim 1, wherein the one or more floated process model parameters comprise a combination of any two or more characteristics of a substrate undergoing the semiconductor device fabrication operation.

4. The method of claim 1, further comprising, prior to (c), providing an initial profile of a substrate undergoing the semiconductor device fabrication operation, whereby

generating the computationally predicted result of the semiconductor device fabrication operation in (c) uses the initial profile.

5. The method of claim 1, wherein the result of a semiconductor device fabrication operation is a signal produced by interaction of incident electromagnetic radiation with an etched feature, a deposited feature, or a planarized feature.

6. The method of claim 1, wherein generating the computationally predicted result of the semiconductor device fabrication operation comprises:

(i) generating, using the configured process simulation model, a computed etch profile represented by a series of geometric profile coordinates; and

(ii) from the computed etch profile generated in (i), generating a computed reflectance or ellipsometric spectrum by simulating reflection of electromagnetic radiation off of said computed etch profile.

7. The method of claim 6, further comprising:

performing the semiconductor device fabrication operation on a test substrate under the set of process parameter values to produce an etched substrate; and

exposing the etched substrate to incident electromagnetic radiation to produce an experimental reflection spectrum comprising the metrology result.

8. The method of claim 6, further comprising generating one or more additional computed reflectance or ellipsometric spectra.

9. The method of claim 1, wherein the result of a semiconductor device fabrication operation is a profile of an etched feature, a profile of a deposited feature, or a profile of a planarized feature.

10. The method of claim 1, wherein generating the computationally predicted result of the semiconductor device fabrication operation comprises generating, using the configured process simulation model, a computed etch profile represented by etch profile coordinates.

11. The method of claim 10, further comprising:

performing the semiconductor device fabrication operation on a test substrate under the set of process parameter values to produce an etched substrate; and

measuring features of the etched substrate to produce experimental etch profile coordinates comprising the metrology result.

12. The method of claim 11, wherein measuring features of the etched substrate comprises performing microscopy, or optical metrology on the etched substrate.

13. The method of claim 1, wherein the result of a semiconductor device fabrication operation is a set of geometric profile parameters characterizing a geometry of an etched feature, a deposited feature, or a planarized feature.

14. The method of claim 13, wherein the geometric profile parameters are Optical Critical Dimension (“

OCD”

) profile parameters.

15. The method of claim 1, wherein generating the computationally predicted result of the semiconductor device fabrication operation comprises:

(i) generating, using the configured process simulation model, a computed etch profile represented by a series of etch profile coordinates; and

(ii) converting the computed etch profile generated in (i) to a first set of geometric profile parameters characterizing a geometry of the of the computed etch profile.

16. The method of claim 15, further comprising:

performing the semiconductor device fabrication operation on a test substrate under the set of process parameter values to produce an etched substrate;

measuring features of the etched substrate to produce experimental etch profile coordinates; and

converting the experimental etch profile coordinates to a second set of geometric profile parameters characterizing a geometry of the of an etched feature in the etched substrate.

17. The method of claim 1, wherein:

the computationally predicted result generated in (c) comprises a sequence of geometric profiles or profile parameters of a substrate feature computed from the configured process simulation model and corresponding to a sequence of times representing different durations of a substrate subtractive process or a substrate additive process; and

the metrology result of (d) comprises a sequence of geometric profiles or profile parameters of the substrate feature obtained from experimental measurements of a substrate at the different durations of the substrate subtractive process or the substrate additive process.

18. The method of claim 1, further comprising:

(i) configuring the process simulation model with the final values of the one or more floated process model parameters from (g); and

(ii) using the process simulation model configured with the final values of the one or more floated process model parameters from (g) to enable;

determining a pattern of a lithographic mask, and

creating the lithographic mask.

19. The method of claim 1, further comprising:

(i) configuring the process simulation model with the final values of the one or more floated process model parameters from (g);

(ii) using the process simulation model configured with the final values of the one or more floated process model parameters from (g) to enable;

identifying a design of a semiconductor processing apparatus, and

fabricating the semiconductor processing apparatus by using the design of the semiconductor processing apparatus.

20. The method of claim 1, further comprising:

(i) configuring the process simulation model with the final values of the one or more floated process model parameters from (g);

(ii) using the process simulation model configured with the final values of the one or more floated process model parameters from (g) to identify operating conditions of a semiconductor processing apparatus to enable fabrication of semiconductor devices by operating the semiconductor processing apparatus under the operating conditions.

21. The method of claim 1, wherein generating the computationally predicted result comprises using the configured process simulation model to calculate local reaction rates at a grid of points representing a feature profile on a semiconductor substrate.

22. A computer program product comprising a non-transitory computer readable medium on which is provided instructions for causing a computational system to execute an optimized process simulation model that calculates a result of a semiconductor device fabrication operation from process parameter values characterizing the semiconductor device fabrication operation, wherein the instructions comprise instructions for:

(a) receiving process parameter values as inputs to the optimized process simulation model;

(b) executing the optimized process simulation model using the process parameter values, wherein the optimized process simulation model was optimized by;

(i) receiving current values of one or more floated process model parameters to be optimized, wherein the one or more floated process model parameters comprise a reaction rate constant, a reactant and/or product sticking coefficient, a reactant diffusion constant, a product diffusion constant, an optical dispersion property, a vertical etch rate, a lateral etch rate, a nominal etch depth, an etch selectivity, a tilt angle of ion entry, a twist angle of ion entry, a visibility into a feature, an angular distribution, a sputter maximum yield angle, an etch ratio per crystal direction, or a combination of these,

(ii) producing a configured process simulation model by providing to the process simulation model the current values of the one or more floated process model parameters and a set of fixed process model parameter value(s),

(iii) generating, using the configured process simulation model, a computationally predicted result of the semiconductor device fabrication operation,

(iv) comparing the computationally predicted result of the semiconductor device fabrication operation with a metrology result obtained from one or more substrate features produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under the set of fixed process parameter values, wherein the comparing produces one or more cost values based on a difference between the computationally predicted result of the semiconductor device fabrication operation and the metrology result,

(v) using the one or more cost values and/or a convergence check to generate an update of the current values of the one or more floated process model parameters,

(vi) performing operation (ii) with the update of the current values of the one or more floated process model parameters, and

(vii) repeating (iii)-(vi) until the current values of the one or more floated process model parameters converge to produce final values of the one or more floated process model parameters that minimize the cost values; and

(c) outputting a calculated result of the semiconductor device fabrication operation.

23. The computer program product of claim 22, wherein the instructions further comprise instructions for, prior to (b), receiving an initial profile of a substrate undergoing the semiconductor device fabrication operation.

24. The computer program product of claim 22, wherein (ii) producing a configured process simulation model further comprises providing to the process simulation model a profile of a substrate before the substrate is subjected to the semiconductor device fabrication operation, wherein the profile of the substrate has one or more features that are to be modified by the semiconductor device fabrication operation.

25. The computer program product of claim 22, wherein the result of a semiconductor device fabrication operation is a signal produced by interaction of incident electromagnetic radiation with an etched feature, a deposited feature, or a planarized feature.

26. The computer program product of claim 22, wherein generating the computationally predicted result of the semiconductor device fabrication operation comprises:

generating, using the configured process simulation model, a computed etch profile represented by a series of geometric profile coordinates; and

from the computed etch profile, generating a computed reflectance or ellipsometric spectrum by simulating reflection of electromagnetic radiation off of said computed etch profile.

27. The computer program product of claim 22, wherein generating the computationally predicted result of the semiconductor device fabrication operation comprises generating, using the configured process simulation model, a computed etch profile represented by etch profile coordinates.

28. The computer program product of claim 22, wherein the result of a semiconductor device fabrication operation is a set of geometric profile parameters characterizing a geometry of an etched feature, a deposited feature, or a planarized feature.

29. The computer program product of claim 28, wherein the geometric profile parameters are Optical Critical Dimension (“

OCD”

) profile parameters.

30. The computer program product of claim 22, further comprising instructions for using the calculated result to determine a pattern of a lithographic mask.

31. The computer program product of claim 22, further comprising instructions for using the calculated result to identify a design of a semiconductor processing apparatus.

32. The computer program product of claim 22, further comprising instructions for using the calculated result to identify operating conditions of a semiconductor processing apparatus to enable fabrication of semiconductor devices by operating the semiconductor processing apparatus under the operating conditions.

33. A system comprising the computer program product of claim 22 and a lithography mask generating apparatus configured to determine a lithographic mask pattern using the calculated result of the semiconductor device fabrication operation.

34. A system comprising the computer program product of claim 22 and a semiconductor processing apparatus configured to operate under process conditions provided in the calculated result of the semiconductor device fabrication operation.