Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models
First Claim
1. A method for generating a memory program pulse in a neuromorphic memory circuit, the neuromorphic memory circuit including a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell, the method comprising:
- generating a presynaptic STDP pulse based on a target spike timing dependent plasticity (STDP) behavior function h(Δ
t) and a memory cell characteristic function fVD1(VA1), the target STDP behavior function h(Δ
t) describing a desired relative change in a synaptic weight of the resistive memory cell based on Δ
t, the memory cell characteristic function fVD1(VA1) describing a relationship between change in an electrical resistance of the resistive memory cell and VA1 at a constant VD1, where Δ
t=t2−
t1, where t1 is a time when the presynaptic neuron circuit fires, where t2 is a time when the postsynaptic neuron circuit fires, where VA1 is a voltage of a presynaptic STDP pulse, where VD1 is an amplitude of a postsynaptic STDP pulse, where the presynaptic STDP pulse is equal to fVD1−
1(h(t+min(Δ
t)−
t1)), and where t is time and min(Δ
t) is a constant time shift; and
transmitting the presynaptic STDP pulse on a presynaptic STDP line, the presynaptic STDP pulse controlling a current flow through the resistive memory cell when the postsynaptic STDP pulse is generated at t2-min(Δ
t).
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Abstract
A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t1. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.
7 Citations
4 Claims
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1. A method for generating a memory program pulse in a neuromorphic memory circuit, the neuromorphic memory circuit including a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell, the method comprising:
-
generating a presynaptic STDP pulse based on a target spike timing dependent plasticity (STDP) behavior function h(Δ
t) and a memory cell characteristic function fVD1(VA1), the target STDP behavior function h(Δ
t) describing a desired relative change in a synaptic weight of the resistive memory cell based on Δ
t, the memory cell characteristic function fVD1(VA1) describing a relationship between change in an electrical resistance of the resistive memory cell and VA1 at a constant VD1, where Δ
t=t2−
t1, where t1 is a time when the presynaptic neuron circuit fires, where t2 is a time when the postsynaptic neuron circuit fires, where VA1 is a voltage of a presynaptic STDP pulse, where VD1 is an amplitude of a postsynaptic STDP pulse, where the presynaptic STDP pulse is equal to fVD1−
1(h(t+min(Δ
t)−
t1)), and where t is time and min(Δ
t) is a constant time shift; andtransmitting the presynaptic STDP pulse on a presynaptic STDP line, the presynaptic STDP pulse controlling a current flow through the resistive memory cell when the postsynaptic STDP pulse is generated at t2-min(Δ
t). - View Dependent Claims (2, 3, 4)
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Specification
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- Resources
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Current AssigneeSamsung Electronics Co. Ltd.
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Original AssigneeInternational Business Machines Corporation
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InventorsHosokawa, Kohji, Ishii, Masatoshi, Kim, SangBum, Lam, Chung H., Lewis, Scott C.
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Primary Examiner(s)King, Douglas
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Application NumberUS14/749,331Publication NumberTime in Patent Office1,707 DaysField of SearchNoneUS Class CurrentCPC Class CodesG06N 3/049 Temporal neural networks, e...G06N 3/065 Analogue meansG06N 3/088 Non-supervised learning, e....
