Display apparatus

• US 10,573,239 B2
• Filed: 08/31/2018
• Issued: 02/25/2020
• Est. Priority Date: 10/19/2012
• Status: Active Grant

• Current Assignee: Japan Display Incorporated
• Original Assignee: Japan Display Incorporated
• Inventors: Omata, Kazuyoshi, Kimura, Hiroyuki, Shibusawa, Makoto, Tabatake, Hiroshi
• Primary Examiner(s): Zheng, Xuemei
• Application Number:
  US16/119,655
• Publication Number:
  US 20180374414A1
• Time in Patent Office: 543 Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0452 Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/325 the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H05B 45/60 Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/351 : comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
• CPC Class Codes: Y02B 20/30 : Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

According to one embodiment, a display apparatus includes a plurality of semiconductor layers, a first insulation film, a first conductive layer, a second insulation film and a display element includes a second conductive layer. The first conductive layer and the second conductive layer are opposed to each other to form a capacitance unit.

Claims

1. A display device having a plurality of pixels comprising:

a semiconductor layer;

a first insulation layer on the semiconductor layer;

a first conductive layer on the first insulation layer;

a second insulation layer on the first insulation layer and the first conductive layer;

a second conductive layer on the second insulation layer;

a third insulation layer on the second insulation layer and the second conductive layer;

a third conductive layer on the third insulation layer; and

a partition insulation layer on the third insulation layer and the third conductive layer;

wherein;

each of the plurality of pixels comprises;

a scanning line;

a video signal line intersecting the scanning line;

a display element between a high-potential power supply line and a low-potential power supply line; and

a drive transistor between the high-potential power supply line and the display element, configured to control a current value from the high-potential power supply line to the display element,

one of electrodes of the display element is formed in the third conductive layer,

a channel of the drive transistor is formed in the semiconductor layer,

a gate of the drive transistor is formed in the first conductive layer,

the partition insulation layer covers an edge of the one of electrodes of the display element, and includes an opening exposing a part of an upper surface of the one of electrodes of the display element,

the opening, the second conductive layer, and the gate of the drive transistor overlap in the plane view,

the second conductive layer extends between adjacent two pixels in the plurality of pixels continuously, and

the second conductive layer intersects the video signal line.

2. The display device according to claim 1, wherein

the second conductive layer extends so as not to be in contact with the gate, and a source and a drain of the drive transistor.

3. The display device according to claim 1, wherein

the high-potential power supply line is configured to be supplied with a high potential,

the low-potential power supply line is configured to be supplied with a low potential having lower than the high potential, and

the second conductive layer is configured to be supplied with one of the high potential and the low potential.

4. The display device according to claim 1, further comprising:

an output switch between the high-potential power supply line and the drive transistor,

wherein

the output switch is configured to select whether to supply the current from the high-potential power supply line to the display element, and

the output switch is configured to be controlled by a signal different from that of the drive transistor.

5. The display device according to claim 4, wherein

a channel of the output switch is further formed in the semiconductor layer.

6. The display device according to claim 1, wherein

the scanning line is formed in the first conductive layer, and

the second conductive layer intersects the scanning line.