Apparatus and methods for triggering row hammer address sampling

• US 10,573,370 B2
• Filed: 07/02/2018
• Issued: 02/25/2020
• Est. Priority Date: 07/02/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ito, Yutaka, He, Yuan
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US16/025,844
• Publication Number:
  US 20200005857A1
• Time in Patent Office: 603 Days
• Field of Search: 365236
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 2211/4065 Low level details of refresh operations

Abstract

Apparatuses and methods for triggering row hammer address sampling are described. An example apparatus includes an oscillator circuit configured to provide a clock signal, and a filter circuit. The filter circuit includes a control circuit configured to receive pulses of the clock signal and provide an output signal that represents a count number by counting a number of pulses of the clock signal and control a probability of enabling the output signal based on the count number. The filter circuit further includes a logic gate configured to pass one of the pulses of the clock signal responsive to the output signal from the control circuit being enabled and filter another of the pulses responsive to the output signal from the control circuit being not enabled.

Claims

1. An apparatus comprising:

an oscillator circuit configured to provide a clock signal; and

a filter circuit including;

a control circuit configured to receive pulses of the clock signal and provide an output signal that represents a count number by counting a number of pulses of the clock signal and control a probability of enabling the output signal based on the count number; and

a logic gate configured to pass one of the pulses of the clock signal responsive to the output signal from the control circuit being enabled and filter another of the pulses

responsive to the output signal from the control circuit being not enabled.

2. The apparatus of claim 1, wherein the control circuit is configured to decrease the probability of enabling the output signal as the count number increases.

3. The apparatus of claim 2, wherein the control circuit is configured to control the probability of enabling the output signal to be I/N, and wherein N is the count number which is an integer equal to or larger than 1.

4. The apparatus of claim 1, wherein the control circuit includes a counter circuit to provide the count number and a pseudo-random number generation circuit to provide an additional number, and wherein the output signal is enabled in detection that the count number becomes a divisor of the additional number and not enabled in detection that the count number does not become the divisor of the additional number.

5. The apparatus of claim 4, wherein the pseudo-random number generation circuit is configured to update the additional number to a further additional number responsive, at least in part, to a row active command.

6. The apparatus of claim 1, wherein the control circuit includes a counter circuit to provide the count number as a first count number and an additional counter circuit configured to circulate a second count number within a range of the first count number, and wherein the output signal is enabled in detection that the second count number becomes a specified number in the range of the first count number and not enabled in detection that the second count number becomes one of the other numbers within the range of the first count number.

7. The apparatus of claim 1, further comprising a refresh control circuit configured to capture a row address input with a row active command responsive to the one of the pulses of the clock signal passed through the logic gate and perform a refresh operation on the row address.

8. A method comprising:

receiving a plurality of pulses of a clock signal at a sampling timing generator circuit of a memory;

adjusting a count value in response each pulse of the plurality of pulses of the clock signal;

setting an output signal based on the count value, wherein a probability of setting the output signal is based on the count value; and

providing a pulse of the plurality of pulses of the clock signal in response to the output signal being set.

9. The method of claim 8, wherein the probability of setting the output signal is 1 divided by the count value.

10. The method of claim 8, further comprising providing a pseudo-random number via a pseudo-random number generator, wherein the output signal is set in response to the count value being a divisor of the pseudo-random number.

11. The method of claim 10, further comprising adjusting the pseudo-random number in response to a row active command or a refresh command.

12. The method of claim 8, further comprising providing a second count value via a second counter;

wherein the output signal is set in response to the second count value being equal to the count value.