Methods of programming memory devices

• US 10,573,378 B2
• Filed: 10/13/2017
• Issued: 02/25/2020
• Est. Priority Date: 06/22/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shim, Young-Seop, Kim, Jae-Hong, Han, Jin-Man
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Radke, Jay W.
• Application Number:
  US15/783,040
• Publication Number:
  US 20180040368A1
• Time in Patent Office: 865 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

Methods of operating non-volatile memory devices are provided including receiving program data and a program address. Memory cells that correspond to the program address are selected from among memory cells in an erased state. The selected memory cells are programmed based on the program data such that each of the selected memory cells is programmed to one of a plurality of programmed states, where threshold voltage distributions of the programmed states are different from each other and are higher than a threshold voltage distribution associated with the erased state. By programming all or a portion of the memory cells corresponding to the erased state to have positive threshold voltages, degradation of the data retention capability of the memory cells may be reduced.

Claims

1. A method of programming a three dimensional non-volatile memory device, the three dimensional non-volatile memory device including a plurality of memory cell strings, each cell string including a plurality of memory cells stacked serially in a direction perpendicular to a substrate, the method comprising:

performing a first erase operation on first memory cells and a second erase operation on second memory cells disposed in a memory cell array, the first memory cells and the second memory cells being erased to a first erased state and a second erased state, respectively, the first erased state being higher in voltage level than the second erased state;

performing a single level cell (SLC) programming operation on the first memory cells, each of the first memory cells being programmed to one of two programmed states, each of the two programmed states being higher in voltage level than the first erased state and each having a different threshold voltage distribution; and

performing a multi-level cell (MLC) programming operation on the second memory cells, a first portion of the second memory cells remaining in the second erased state, a second portion of the second memory cells being programmed to one of at least three programmed states, each of the at least three programmed states being higher in voltage level than the second erased state and each having a different threshold voltage distribution,

wherein a lowest programmed state of the first memory cells has a first threshold voltage distribution and the second erased state of the second memory cells has a second threshold voltage distribution, the first threshold voltage distribution being substantially positioned at positive voltage level while the second threshold voltage distribution is substantially positioned at negative voltage level.

2. The method of claim 1, further comprising applying a positive verification voltage after performing the first erase operation to verify that at least a portion of the first memory cells have positive threshold voltages.

3. The method of claim 2, further comprising programming MLCs to SLCs through the first erase operation and the SLC programming operation.

4. The method of claim 3, further comprising preprogramming MLCs into SLCs in the SLC programming operation, the preprogramming being performed after the first erase operation and before the SLC programming operation for preprogrammed memory cells to have positive threshold voltages.

5. The method of claim 1, wherein the lowest programmed state of the first memory cells is programmed using a self-alignment scheme, the self-alignment scheme comprising:

programming a first portion of the first memory cells to a lowest programmed state of the two programmed states, the first portion of the first memory cells being selected for being programmed to the lowest programmed state; and

programming a second portion of the first memory cells to a remaining programmed state of the two programmed states, the second portion of the first memory cells being selected for being programmed to the remaining programmed state,

wherein the remaining programmed state has a threshold voltage distribution that is higher in voltage level than the threshold voltage distribution of the lowest programmed state.

6. The method of claim 1:

wherein at least one verification voltage is used for the SLC programming operation generated by a voltage generator, the at least one verification voltage being supplied to a write circuit; and

wherein at least three verification voltages are generated by the voltage generator and are supplied to the write circuit for the MLC programming operation.

7. The method of claim 1:

wherein the first memory cells are disposed in a main region of the memory cell array and the second memory cells are disposed in a spare region of the memory cell array; and

wherein the main region stores user data and the spare region stores additional data, the additional data including at least one of flag information, error correction code, device code, maker code, and page information.

8. The method of claim 7, wherein the main region and the spare region of the memory cell array are interchanged, a portion of main region is changed to the spare region and/or a portion of spare region is changed to the main region.

9. A method of programming a non-volatile memory device, the method comprising:

performing a first erase operation on first memory cells and a second erase operation on second memory cells disposed in a memory cell array, the first memory cells and the second memory cells being erased to a first erased state and a second erased state, respectively, the first erased state being higher in voltage level than the second erased state;

performing a single level cell (SLC) programming operation on the first memory cells, each of the first memory cells being programmed to one of two programmed states, each of the two programmed states being higher in voltage level than the first erased state and each having a different threshold voltage distribution; and

performing a multi-level cell (MLC) programming operation on the second memory cells, a first portion of the second memory cells remaining in the second erased state, a second portion of the second memory cells being programmed to one of at least three programmed states, each of the at least three programmed states being higher in voltage level than the second erased state and each having a different threshold voltage distribution,

wherein a lowest programmed state of the first memory cells has a first threshold voltage distribution and the second erased state of the second memory cells has a second threshold voltage distribution, the first threshold voltage distribution is higher in voltage level than the second threshold voltage distribution.

10. The method of claim 9, further comprising applying a positive verification voltage after performing the first erase operation to verify that at least a portion of the first memory cells have positive threshold voltages.

11. The method of claim 10, wherein the first threshold voltage distribution is substantially positioned at positive voltage level while the second threshold voltage distribution is substantially positioned at negative voltage level.

12. The method of claim 11, further comprising:

generating two verification voltages at a voltage generator and supplying the two verification voltages to a write circuit for the SLC programming operation; and

generating at least three verification voltages at the voltage generator and supplying the at least three verification voltages to the write circuit for the MLC programming operation.

13. The method of claim 12, wherein the non-volatile memory device is a three dimensional non-volatile memory device comprising a plurality of memory cell strings, each cell string including multiple memory cells stacked serially in a direction perpendicular to a substrate.

14. The method of claim 13, wherein the first memory cells are disposed in a main region of the memory cell array and the second memory cells are disposed in a spare region of the memory cell array.

15. The method of claim 14, wherein the main region stores user data and the spare region stores additional data, the additional data including at least one of flag information, error correction code, device code, maker code, and page information.

16. The method of claim 15, wherein the main region and the spare region of the memory cell array are interchanged, a portion of main region is changed to the spare region, and/or a portion of spare region is changed to the main region.

17. The method of claim 16, wherein the method further includes preprogramming MLCs into SLCs in the SLC programming operation, the preprogramming being performed after the first erase operation and before performing the SLC programming operation for the first memory cells to have positive threshold voltages.

18. The method of claim 17, wherein the lowest programmed state of the first memory cells is programmed using a self-alignment scheme, the self-alignment scheme comprising:

programming a first portion of the first memory cells to a lowest programmed state of the two programmed states, the first portion of the first memory cells being selected for being programmed to the lowest programmed state; and

programming a second portion of the first memory cells to a remaining programmed state of the two programmed states, the second portion of the first memory cells being selected for being programmed to the remaining programmed state,

wherein the remaining programmed state has a threshold voltage distribution that is higher in voltage level than the threshold voltage distribution of the lowest programmed state.

19. The method of claim 9, wherein both the first threshold voltage distribution and the second threshold voltage distribution are substantially positioned at positive voltage level.

20. The method of claim 9, wherein the first memory cells are less affected by an erase-to-program interval (EPI) than the second memory cells.