Semiconductor device package and method of manufacturing the same

• US 10,573,624 B2
• Filed: 11/16/2018
• Issued: 02/25/2020
• Est. Priority Date: 03/09/2017
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chen, Tien-Szu, Chen, Kuang-Hsiung, Wang, Sheng-Ming, Wang, I-Cheng, Syu, Wun-Jheng
• Primary Examiner(s): Clark, Jasmine J
• Application Number:
  US16/194,265
• Publication Number:
  US 20190088626A1
• Time in Patent Office: 466 Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/24 : solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/29 : characterised by the material , e.g. carbon interlayer dielectrics H01L23/5329
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1533 : the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.

Claims

1. A semiconductor device package, comprising:

a first circuit layer including a first surface and a second surface opposite to the first surface;

at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer;

a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element;

a plurality of first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and

a second molding layer disposed over the second surface of the first circuit layer and encapsulating the plurality of first electronic components, wherein the first molding layer and the second molding layer include different molding materials.

2. The semiconductor device package of claim 1, further comprising:

a second circuit layer disposed over the second molding layer; and

at least one first interconnect disposed between the first circuit layer and the second circuit layer, encapsulated by the second molding layer, and electrically connected to the first circuit layer and the second circuit layer.

3. The semiconductor device package of claim 2, further comprising a package stacked over and electrically connected to the second circuit layer.

4. The semiconductor device package of claim 3, wherein the package comprises at least one second electronic component disposed over and electrically connected to the second circuit layer.

5. The semiconductor device package of claim 4, wherein the package further comprises a third molding layer disposed over the second circuit layer and encapsulating the at least one second electronic component, and the first molding layer, the second molding layer and the third molding layer include different molding materials.

6. The semiconductor device package of claim 4, wherein the package further comprises at least one second interconnect disposed over and electrically connected to the second circuit layer.

7. A semiconductor device package, comprising:

a first circuit layer including a first surface and a second surface opposite to the first surface;

at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer;

a first molding layer disposed over the first surface of the first circuit layer and encapsulating the at least one electrical element;

at least one first electronic component disposed over the second surface of the first circuit layer, wherein the at least one first electronic component further comprises a plurality of conductors;

a second molding layer disposed over the second surface of the first circuit layer and encapsulating the at least one first electronic component;

a second circuit layer disposed over the second molding layer, wherein the plurality of conductors face the second circuit layer, and electrically connect the at least one first electronic component to the second circuit layer;

at least one first interconnect disposed between the first circuit layer and the second circuit layer, encapsulated by the second molding layer, and electrically connected to the first circuit layer and the second circuit layer; and

at least one second electronic component disposed over and electrically connected to the second circuit layer.

8. The semiconductor device package of claim 7, further comprising a third molding layer disposed over the second circuit layer and encapsulating the at least one second electronic component.

9. The semiconductor device package of claim 8, further comprising at least one second interconnect disposed over and electrically connected to the second circuit layer.

10. The semiconductor device package of claim 9, wherein the at least one second interconnect is laterally surrounded by the third molding layer.

11. The semiconductor device package of claim 10, wherein an end of the at least one second interconnect is exposed from the third molding layer.

12. The semiconductor device package of claim 7, wherein the at least one first electronic component is electrically connected to the first circuit layer through the second circuit layer and the at least one first interconnect.

13. The semiconductor device package of claim 7, further comprising an adhesive layer disposed between and bonded to the first circuit layer and the at least one first electronic component.

14. A method of manufacturing a semiconductor device package, comprising:

providing a carrier;

forming at least one electrical element over the carrier;

forming a first molding layer over the carrier to encapsulate the at least one electrical element;

removing the carrier from the at least one electrical element and the first molding layer;

forming a first circuit layer over the first molding layer;

disposing at least one first electronic component over the first circuit layer; and

forming a second molding layer over the first circuit layer to encapsulate the at least one first electronic component.

15. The method of claim 14, further comprising:

forming at least one electrical contact over a lower surface of the at least one electrical element.

16. The method of claim 15, further comprising removing a portion of the first molding layer and a portion of the at least one electrical element to expose the lower surface of the at least one electrical element, wherein the lower surface of the at least one electrical element and a lower surface of the first molding layer are substantially coplanar.

17. The method of claim 14, further comprising:

forming at least one first interconnect over the first circuit layer prior to forming the second molding layer; and

forming a second circuit layer over the second molding layer.

18. The method of claim 17, wherein the at least one first electronic component further comprises a plurality of conductors facing and electrically connected to the second circuit layer, and the at least one first electronic component is electrically connected to the first circuit layer through the second circuit layer and the at least one first interconnect.

19. The method of claim 17, further comprising:

disposing at least one second electronic component over and electrically connected to the second circuit layer;

forming at least one second interconnect over and electrically connected to the second circuit layer; and

forming a third molding layer over the second circuit layer to encapsulate the at least one second electronic component and the least one second interconnect.