Tipless transistors, short-tip transistors, and methods and circuits therefor

• US 10,573,644 B2
• Filed: 03/27/2018
• Issued: 02/25/2020
• Est. Priority Date: 12/09/2011
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Kidd, David A.
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US15/936,724
• Publication Number:
  US 20180226401A1
• Time in Patent Office: 700 Days
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/365 Planar doping, e.g. atomic-plane doping, delta-doping
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence
• CPC Class Codes: H03K 5/05 by the use of clock signals or other time reference signals
• CPC Class Codes: H03K 5/06 by the use of delay lines or other analogue delay elements
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/081 : provided with an additional controlled phase shifter H03L7/0998 takes precedence

Abstract

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

Claims

1. An integrated circuit, comprising:

a plurality of first deeply depleted channel (DDC) transistors formed in a substrate and having controllable source-drain current paths coupled between a first and second node, the first DDC transistors having a first source drain vertical doping profile with first extension regions that extends in a lateral direction under a gate electrode of the first DDC transistors, the first DDC transistors being configured to selectively couple a first output node to the first or second node in response to one or more input signals, the first DDC transistors having drawn gate lengths of less than one micron;

a plurality of second deeply depleted channel (DDC) transistors formed in the substrate and having controllable source-drain current paths coupled between the first node and the second node, the second DDC transistors having a second source drain vertical doping profile with second extension regions that extends in a lateral direction under a gate electrode of the second DDC transistors, the second source drain vertical doping profile having less dopant concentration than the first source drain vertical doping profile, the second DDC transistors being configured to selectively couple a second output node to the first or second node in response to the one or more input signals, the second DDC transistors having drawn gate lengths of less than one micron.

2. The integrated circuit of claim 1, wherein:

the first deeply depleted channel transistor having a first source and drain having the first source drain vertical doping profile doped to a first conductivity type, a first substantially undoped channel region, and a first highly doped screening region of the second conductivity type formed below the first substantially undoped channel region.

3. The integrated circuit of claim 1, wherein:

the second deeply depleted channel transistor having a second source and drain having the second source drain vertical doping profile doped to a first conductivity type, a second substantially undoped channel region, and a second highly doped screening region of the second conductivity type formed below the second substantially undoped channel region.

4. The integrated circuit of claim 1, further including:

a delay circuit configured to delay an electrical signal and comprising at least the second deeply depleted channel transistor.

5. The integrated circuit of claim 4, further including:

a logic gate configured to logically combine signals at a plurality of gate inputs to generate a gate output signal; and

the delay circuit is coupled to a first gate input of the logic gate.

6. The integrated circuit of claim 5, further including:

a pulse generator that includes the logic gate having a second gate input coupled to receive an input signal, and

the delay circuit is coupled to receive the input signal and has a delay circuit output coupled to the first gate input.

7. The integrated circuit of claim 6, wherein:

the pulse generator further includes the logic gate having a third gate coupled to receive an enable signal that enables and disables the pulse generator circuit.

8. The integrated circuit of claim 6, further including:

a flip-flop circuit comprising a plurality of latches arranged in series, each latch having a clocked input,

passgates coupled in parallel to an input of the flip-flop circuit, and

the delay circuit is coupled to an input of one of the passgates.

9. The integrated circuit of claim 6, further including:

a memory cell array;

sense amplifier circuits coupled to the memory cell array and configured to sense data values from memory cells of the memory cell array, the sense amplifier circuits being enabled in response to a sense amplifier control signal;

a control circuit configured to generate an initial sense amplifier control signal; and

the delay circuit is configured to delay the initial sense amplifier control signal to generate the sense amplifier control signal.

10. The integrated circuit of claim 5, further including:

a timing control circuit configured to generate a periodic timing clock for the integrated circuit, and comprising the delay circuit;

wherein

the timing control circuit is selected from the group of;

a phase locked loop circuit and a delay locked loop circuit.

11. The integrated circuit of claim 1, wherein:

the first deeply depleted channel transistor has the first drawn gate length of less than 0.5 micron; and

the second deeply depleted channel transistor has the second drawn gate length of less than 0.5 micron.

12. The integrated circuit of claim 1, and further comprising:

a plurality of third deeply depleted channel (DDC) transistors formed in the substrate and having controllable source-drain current paths coupled between the first node and the second node, the third DDC transistors having a third source drain vertical doping profile with third extension regions that extends in a lateral direction under a gate electrode of the third DDC transistors, the third source drain vertical doping profile having less dopant concentration than the second source drain vertical doping profile, the third DDC transistors being configured to selectively couple a third output node to the first or second node in response to the one or more input signals, the third DDC transistors having drawn gate lengths of less than one micron.