Horizontal gate all around device isolation

• US 10,573,719 B2
• Filed: 09/28/2016
• Issued: 02/25/2020
• Est. Priority Date: 05/11/2015
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Sun, Shiyu, Yoshida, Naomi, Guarini, Theresa Kramer, Jun, Sung Won, Colombeau, Benjamin, Chudzik, Michael
• Primary Examiner(s): Stark, Jarrett J
• Application Number:
  US15/279,257
• Publication Number:
  US 20170018624A1
• Time in Patent Office: 1,245 Days
• Field of Search: 438437, 438439, 438442, 438452
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/15 Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices such structures applied for the control of light G02F1/017, applied in semiconductor lasers H01S5/34
• CPC Class Codes: H01L 29/157 Doping structures, e.g. doping superlattices, nipi superlattices delta doping in general H01L29/365
• CPC Class Codes: H01L 29/158 Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Claims

1. A method of forming a semiconductor device, comprising:

forming a superlattice structure on a substrate, wherein the superlattice structure comprises;

a silicon containing material layer;

a first silicon germanium material layer having a first germanium content; and

a second silicon germanium material layer having a second germanium content greater than the first germanium content of the first silicon germanium material layer;

etching the superlattice structure;

depositing a liner on the superlattice structure;

depositing an oxide material layer on the substrate after depositing the liner; and

oxidizing one of the first material layer, the second material layer, or the third material layer to form a buried oxide layer after depositing the oxide material layer, wherein the liner selectively prevents oxidation of two of the material layers preferentially to the material layer which forms the buried oxide.

2. The method of claim 1, wherein the silicon containing material layer and the first silicon germanium material layer are disposed within the superlattice structure in an alternating stacked arrangement.

3. The method of claim 1, wherein the first silicon germanium material layer comprises about 70% silicon and about 30% germanium, and the second silicon germanium material layer comprises about 30% silicon and about 70% germanium.

4. The method of claim 1, wherein the first silicon germanium material layer is disposed on the substrate and the second silicon germanium material layer is disposed on the second material layer.

5. The method of claim 1, wherein the substrate comprises a silicon containing material.

6. The method of claim 1, wherein depositing the liner comprises:

performing a chemical vapor deposition nitridation process.

7. The method of claim 1, wherein depositing the liner comprises:

performing an atomic layer deposition nitridation process.

8. The method of claim 1, wherein depositing the oxide material layer comprises:

performing a flowable chemical vapor deposition process to deposit the oxide material layer.

9. The method of claim 1, wherein the oxidizing comprises:

performing a steam annealing process at a temperature of between about 300°

C. and about 800°

C.

10. The method of claim 9, further comprising:

performing a dry annealing process after the steam annealing process, the dry annealing process performed at a temperature of between about 500°

C. and about 1000°

C.

11. A method of forming a semiconductor device, comprising:

forming a superlattice structure on a substrate, wherein the superlattice structure comprises;

a silicon material layer;

a low germanium content silicon germanium material layer; and

a high germanium content silicon germanium material layer;

etching the superlattice structure;

depositing a nitride liner on the superlattice structure;

depositing an oxide material layer on the substrate; and

oxidizing the high germanium content silicon germanium material layer to form a buried oxide layer, wherein the nitride liner selectively prevents oxidation of the silicon material layer and the low germanium content silicon germanium layer.

12. The method of claim 11, wherein the silicon material layer and the low germanium content silicon germanium material layer are disposed within the superlattice structure in an alternating stacked arrangement.

13. The method of claim 11, wherein the low germanium content material layer comprises about 70% silicon and about 30% germanium and the high germanium content material layer comprises about 30% silicon and about 70% germanium.

14. The method of claim 12, wherein the high germanium content silicon germanium material layer is disposed on the substrate.

15. The method of claim 12, wherein the low germanium content silicon germanium material layer is disposed on the substrate and the high germanium content material layer is disposed on the low germanium content material layer.

16. The method of claim 11, wherein oxidizing the high germanium content silicon germanium material layer comprises:

performing a steam annealing process at a temperature of between about 300°

C. and about 800°

C.; and

performing a dry annealing process after the steam annealing process at a temperature of between about 500°

C. and about 1000°

C.

17. A method of forming a semiconductor device, comprising:

forming a superlattice structure on a substrate, wherein the superlattice structure comprises;

a silicon material layer;

a first silicon germanium material layer comprising about 30% germanium; and

a second silicon germanium material layer comprising about 70% germanium, wherein the silicon material layer, the first silicon germanium material layer, and the second silicon germanium layer are disposed in a stacked arrangement;

depositing a nitride liner on the superlattice structure;

depositing an oxide material layer on the substrate; and

oxidizing the second silicon germanium material layer to form a buried oxide layer, wherein the nitride liner selectively prevents oxidation of the silicon material layer and the first silicon germanium material layer.

18. The method of claim 17, wherein oxidizing the second silicon germanium material layer comprises:

performing a steam annealing process at a temperature of between about 300°

C. and about 800°

C.

19. The method of claim 18, further comprising:

performing a dry annealing process after the steam annealing process at a temperature of between about 500°

C. and about 1000°

C.