Oxygen inserted Si-layers in vertical trench power devices

• US 10,573,742 B1
• Filed: 08/08/2018
• Issued: 02/25/2020
• Est. Priority Date: 08/08/2018
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Feil, Thomas, Haase, Robert, Poelzl, Martin, Roesch, Maximilian, Leomant, Sylvain, Goller, Bernhard, Joshi, Ravi Keshav
• Primary Examiner(s): Harrison, Monica D
• Application Number:
  US16/058,655
• Publication Number:
  US 20200052110A1
• Time in Patent Office: 566 Days
• Field of Search: 257330
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0856 Source regions
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate adjacent the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, a diffusion barrier structure formed along the sidewall of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si, and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.

Claims

1. A semiconductor device;

comprising;

a gate trench extending into a Si substrate;

a body region in the Si substrate adjacent the gate trench;

a source region in the Si substrate above the body region;

a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench;

a diffusion barrier structure formed along the sidewall of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; and

a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench.

2. The semiconductor device of claim 1, wherein the diffusion barrier structure extends onto a front main surface of the Si substrate into which the gate trench and the contact trench are formed.

3. The semiconductor device of claim 2, wherein the diffusion barrier structure extends along the front main surface of the Si substrate to the electrically conductive material which fills the contact trench.

4. The semiconductor device of claim 1, wherein the Si capping layer of the diffusion barrier structure is present along a bottom of the gate trench but not the alternating layers of Si and oxygen-doped Si.

5. The semiconductor device of claim 1, wherein the gate trench comprises a gate dielectric lining the sidewall and a bottom of the gate trench, a gate electrode disposed in an upper part of the gate trench, a field electrode embedded in a field dielectric in a lower part of the gate trench below the gate electrode, an insulating spacer vertically separating the gate electrode from the field electrode, and a silicon nitride layer separating the insulating spacer and the field dielectric from the gate dielectric.

6. A method of manufacturing a semiconductor device, the method comprising:

forming a gate trench which extends into a Si substrate;

forming a body region in the Si substrate adjacent the gate trench;

forming a source region in the Si substrate above the body region;

forming a contact trench which extends into the Si substrate and is filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench;

forming a diffusion barrier structure along the sidewall of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; and

forming a channel region in the Si capping layer and which vertically extends along the sidewall of the gate trench.

7. The method of claim 6, wherein forming the diffusion barrier structure comprises:

epitaxially growing the alternating layers of Si and oxygen-doped Si on the sidewall and a bottom of the gate trench; and

epitaxially growing the Si capping layer on the alternating layers of Si and oxygen-doped Si.

8. The method of claim 7, further comprising:

epitaxially growing the alternating layers of Si and oxygen-doped Si and the Si capping layer on a front main surface of the Si substrate into which the gate trench is formed.

9. The method of claim 7, further comprising:

forming a gate dielectric on the Si capping layer.

10. The method of claim 9, wherein the gate dielectric is formed by a deposition process;

a thermal oxidation process, or both the deposition process and the thermal oxidation process.

11. The method of claim 9, further comprising:

forming a silicon nitride layer on the gate dielectric;

forming a field dielectric on the silicon nitride layer;

after forming the field dielectric, filling the gate trench with a first electrically conductive material; and

recessing the first electrically conductive material to a first depth in the gate trench to form a field electrode.

12. The method of claim 11, further comprising:

removing the field dielectric above the field electrode to expose the silicon nitride layer in a region of the gate trench above the field electrode; and

after removing the field dielectric above the field electrode, covering the field electrode with an insulating spacer.

13. The method of claim 12, wherein covering the field electrode with the insulating spacer comprises:

after removing the field oxide above the field electrode, filling the gate trench with a dielectric material; and

recessing the dielectric material to a second depth in the gate trench above the field electrode.

14. The method of claim 13, wherein filling the gate trench with the dielectric material comprises:

depositing a high-density-plasma oxide in the gate trench by chemical vapor deposition.

15. The method of claim 12, wherein covering the field electrode with the insulating spacer comprises:

forming a thermal oxide on the field electrode by a thermal oxidation process.

16. The method of claim 12, further comprising:

removing the silicon nitride layer above the insulating spacer;

after removing the silicon nitride layer above the insulating spacer, filling the gate trench with a second electrically conductive material; and

recessing the second electrically conductive material to a third depth in the gate trench to form a gate electrode.

17. The method of claim 16, further comprising, after forming the gate electrode, implanting dopant species of the opposite conductivity type into the Si substrate to form the body and the source regions.

18. The method of claim 17, wherein the contact trench is formed after implanting the dopant species of the opposite conductivity type into the Si substrate.

19. The method of claim 12, further comprising:

removing the silicon nitride layer above the insulating spacer;

after removing the silicon nitride layer above the insulating spacer, filling the gate trench with a second electrically conductive material; and

recessing the second electrically conductive material to a third depth in the gate trench to form a gate electrode.

20. The method of claim 12, further comprising:

before forming the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure, forming an insulating spacer in a lower part of the gate trench, the insulating spacer covering a bottom and a lower part of the sidewall of the gate trench to prevent formation of the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure on the bottom and the lower part of the sidewall of the gate trench; and

after forming the alternating layers of Si and oxygen-doped Si of the diffusion barrier structure, removing the insulating spacer from the lower part of the gate trench.

21. The method of claim 20, further comprising:

after removing the insulating spacer from the lower part of the gate trench, epitaxially growing the Si capping layer of the diffusion barrier structure on the alternating layers of Si and oxygen-doped Si and on the bottom and the lower part of the sidewall of the gate trench.

22. The method of claim 20, wherein forming the insulating spacer in the lower part of the gate trench comprises:

forming a high-density plasma oxide on the sidewall and the bottom of the gate trench, the high-density plasma oxide being thinner along the sidewall and thicker on the bottom of the gate trench; and

removing the high-density plasma oxide from the sidewall of the gate trench.

23. The method of claim 20, wherein forming the insulating spacer in the lower part of the gate trench comprises:

forming a silicon oxide layer on the sidewall and the bottom of the gate trench;

forming a silicon nitride layer on the silicon oxide layer over the sidewall and the bottom of the gate trench;

forming an opening in the silicon nitride layer at the bottom of the gate trench to expose the silicon oxide layer at the bottom of the gate trench;

thermally oxidizing a region of the Si substrate below the exposed silicon oxide layer at the bottom of the gate trench; and

removing the silicon nitride layer and the silicon oxide layer from the sidewall of the gate trench.

24. The method of claim 6, further comprising, after forming the diffusion barrier structure, implanting dopant species of the opposite conductivity type into the Si substrate to form the body and the source regions.