Super long channel device within VFET architecture

• US 10,573,745 B2
• Filed: 05/23/2017
• Issued: 02/25/2020
• Est. Priority Date: 05/23/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bergendahl, Marc A., Cheng, Kangguo, Karve, Gauri, Lie, Fee Li, Miller, Eric R., Sporre, John R., Teehan, Sean
• Primary Examiner(s): Fan, Bo
• Application Number:
  US15/602,884
• Publication Number:
  US 20180342614A1
• Time in Patent Office: 1,008 Days
• Field of Search: 438212, 257623, 257401, 257330
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

Claims

1. A semiconductor device, comprising:

a pair of semiconductor fins formed on a substrate;

a semiconductor pillar formed between the semiconductor fins on the substrate;

a bottom doped region that extends under all of the semiconductor fins and under only a part of the semiconductor pillar; and

a conductive gate formed over a channel region of the semiconductor fins and a channel region of the semiconductor pillar;

wherein a source region on a top surface of a first semiconductor fin of the pair of semiconductor fins is electrically coupled to a drain region on a top surface of a second semiconductor fin of the pair of semiconductor fins through the channel region of the semiconductor pillar.

2. The semiconductor device of claim 1 further comprising a thick oxide layer formed between the conductive gate and the semiconductor fins.

3. The semiconductor device of claim 1, wherein the semiconductor pillar is recessed below a surface of the semiconductor fins.

4. The semiconductor device of claim 1 further comprising a bottom spacer between the conductive gate and the bottom doped region.

5. The semiconductor device of claim 1 further comprising a top spacer on the conductive gate.

13. The semiconductor device of claim 1, wherein a width of the pillar is greater a width of the semiconductor fins.

14. The semiconductor device of claim 13, wherein a width of the pillar is at least twice the width of the semiconductor fins.

15. The semiconductor device of claim 1, wherein the semiconductor fins and the pillar are electrically isolated from other regions of the substrate by a shallow trench isolation.

16. The semiconductor device of claim 1 further comprising a blocking region.

17. The semiconductor device of claim 16, wherein the blocking regions is formed below the pillar.

6. A semiconductor device, comprising:

a first semiconductor fin formed on a substrate;

a second semiconductor fin formed on the substrate and adjacent to the first semiconductor fin;

a semiconductor pillar formed between the first and second semiconductor fins;

a bottom doped region that extends under all of the semiconductor fins and under only a part of the semiconductor pillar; and

a shared conductive gate formed over a channel region of the first and second semiconductor fins and a channel region of the semiconductor pillar;

a source region formed on a top surface of the first semiconductor fin; and

a drain region formed on a top surface of the second semiconductor fin;

wherein the source region on the first semiconductor fin is electrically coupled to the drain region on the second semiconductor fin through the channel region of the semiconductor pillar.

7. The semiconductor device of claim 6 further comprising a thick oxide layer formed between the conductive gate and the first and second semiconductor fins, said thick oxide layer also formed between the conductive gate and the semiconductor pillar.

8. The semiconductor device of claim 6, wherein a width of the semiconductor pillar is greater a width of the first and second semiconductor fins.

9. The semiconductor device of claim 8, wherein a width of the semiconductor pillar is at least twice the width of the first and second semiconductor fins.

10. The semiconductor device of claim 6, wherein the first and second semiconductor fins and the semiconductor pillar are electrically isolated from other regions of the substrate by a shallow trench isolation.

11. The semiconductor device of claim 6 further comprising a blocking region.

12. The semiconductor device of claim 11, wherein the blocking regions is formed below the pillar.