Semiconductor device

• US 10,573,757 B2
• Filed: 10/17/2018
• Issued: 02/25/2020
• Est. Priority Date: 09/15/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Higaki, Yoshinari, Sakakura, Masayuki, Yamazaki, Shunpei
• Primary Examiner(s): Wong, Tina M
• Application Number:
  US16/163,052
• Publication Number:
  US 20190115477A1
• Time in Patent Office: 496 Days
• Field of Search: None
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.

Claims

1. A semiconductor device comprising:

a semiconductor layer;

a first conductive layer over and in contact with the semiconductor layer;

a second conductive layer over and in contact with the first conductive layer;

an insulating layer over the second conductive layer; and

a third conductive layer over the insulating layer,

wherein a thickness of the second conductive layer is larger than a thickness of the first conductive layer,

wherein the insulating layer comprises an opening,

wherein a region of the first conductive layer exposed from the opening is in contact with the third conductive layer,

wherein an end portion of the first conductive layer extends beyond an end portion of the second conductive layer, and

wherein an angle between a side surface and a bottom surface of the first conductive layer is smaller than an angle between a side surface and a bottom surface of the second conductive layer.

2. The semiconductor device according to claim 1,

wherein the thickness of the first conductive layer is larger than or equal to 20 nm and smaller than or equal to 200 nm, and

wherein the thickness of the first conductive layer is larger than or equal to 0.1 μ

m and smaller than or equal to 2 μ

m.

3. The semiconductor device according to claim 1,

wherein the first conductive layer comprises titanium or molybdenum.

4. The semiconductor device according to claim 1,

wherein the second conductive layer comprises aluminum.

5. The semiconductor device according to claim 1,

wherein the third conductive layer comprises indium tin oxide, indium tin oxide containing silicon oxide, or indium tin oxide containing silicon oxide in which zinc oxide is mixed.

6. A module comprising the semiconductor device according to claim 1.

7. An electronic device comprising the semiconductor device according to claim 1.