Decoding method for signal processing circuit and signal processing circuit using the same

• US 10,574,095 B2
• Filed: 01/07/2019
• Issued: 02/25/2020
• Est. Priority Date: 02/01/2011
• Status: Active Grant

• Current Assignee: Fu Da Tong Technology Co., Ltd.
• Original Assignee: Fu Da Tong Technology Co., Ltd.
• Inventors: Tsai, Ming-Chiu, Chan, Chi-Che
• Primary Examiner(s): Barnie, Rexford N
• Assistant Examiner(s): Ly, Xuan
• Application Number:
  US16/241,940
• Publication Number:
  US 20190140491A1
• Time in Patent Office: 414 Days
• Field of Search: 307104
• CPC Class Codes: G01R 19/04 Measuring peak values or amplitude or envelope of ac or of pulses
• CPC Class Codes: G01R 31/42 AC power supplies
• CPC Class Codes: H02J 50/12 of the resonant type
• CPC Class Codes: H02J 50/80 involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
• CPC Class Codes: H02J 7/00034 Charger exchanging data with an electronic device, i.e. telephone, whose internal battery is under charge
• CPC Class Codes: H04B 15/00 Suppression or limitation of noise or interference by means associated with receiver H04B1/10
• CPC Class Codes: H04B 5/26 using coils
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A decoding method for a signal processing circuit which receives a modulation data carried by a coil signal includes the following steps: determining a jitter in the coil signal; obtaining a trigger gap when the jitter appears; outputting a gap indicating signal when a length of the trigger gap is within a predefined range; determining whether a plurality of gap indicating signals appear in a first period and whether the gap indicating signals are scattered in the first period; setting a flag to a jitter status according to the above determination results; determining whether the flag is set to the jitter status during a second period, and filling a value in a time slot corresponding to the second period accordingly; and obtaining a data code of the modulation data according to the values filled in a plurality of time slots.

Claims

1. A decoding method for a signal processing circuit, the signal processing circuit receiving a modulation data carried by a coil signal, the decoding method comprising:

receiving the coil signal and determining a jitter in the coil signal;

obtaining a trigger gap when the jitter appears in a peak location of a plurality of peaks in the coil signal;

determining a length of the trigger gap, and outputting a gap indicating signal when the length of the trigger gap is within a predefined range;

determining whether a plurality of gap indicating signals appear in a first period, and determining whether the plurality of gap indicating signals are scattered in the first period;

setting a flag to a jitter status according to determination results of whether the plurality of gap indicating signals appear in the first period and whether the plurality of gap indicating signals are scattered in the first period;

determining whether the flag is set to the jitter status during a second period, and accordingly filling a value in a time slot corresponding to the second period among a plurality of time slots for determining the modulation data; and

obtaining a data code of the modulation data according to a plurality of values filled in the plurality of time slots.

2. The decoding method of claim 1, wherein the steps of receiving the coil signal and determining the jitter in the coil signal and obtaining the trigger gap when the jitter appears in the peak location of the plurality of peaks in the coil signal comprise:

setting a peak voltage level for tracking peak voltages of the plurality of peaks;

decreasing the peak voltage level by a predetermined value to obtain a determination voltage level;

comparing the determination voltage level with the coil signal; and

determining that the trigger gap appears when the peak voltage of a peak among the plurality of peaks smaller than the determination voltage level is detected.

3. The decoding method of claim 1, wherein the first period is divided into a first sub-period and a second sub-period, and the step of determining whether the plurality of gap indicating signals are scattered in the first period comprises:

determining whether at least one of the plurality of gap indicating signals appears in the first sub-period;

determining whether at least one of the plurality of gap indicating signals appears in the second sub-period; and

determining that the plurality of gap indicating signals are scattered in the first period when the plurality of gap indicating signals appear in both of the first sub-period and the second sub-period.

4. The decoding method of claim 1, wherein the step of setting the flag to the jitter status according to the determination results of whether the plurality of gap indicating signals appear in the first period and whether the plurality of gap indicating signals are scattered in the first period comprises:

setting the flag to the jitter status when the gap indicating signals appear in the first period and the gap indicating signals are scattered in the first period.

5. The decoding method of claim 1, wherein the step of determining whether the flag is set to the jitter status during the second period and accordingly filling the value in the time slot corresponding to the second period among the plurality of time slots for determining the modulation data comprises:

filling a first value in the time slot corresponding to the second period when the flag is set to the jitter status; and

filling a second value in the time slot corresponding to the second period when the flag is not set to the jitter status.

6. The decoding method of claim 5, wherein the step of obtaining the data code of the modulation data according to the plurality of values filled in the plurality of time slots comprises:

fetching a first time slot filled with the first value and a second time slot filled with the next first value among the plurality of time slots;

calculating a gap between the first time slot and the second time slot to determine whether the gap complies with a bit length of the data code; and

obtaining the data code according to a length of the gap.

7. The decoding method of claim 6, further comprising:

determining at least one of a start bit and a parity check code of the modulation data according to the gap.

8. The decoding method of claim 7, further comprising:

obtaining the start bit, a byte of data codes and the parity check code of the modulation data during a third period.

9. The decoding method of claim 8, wherein the third period is equal to 50 milliseconds and the second period is equal to 0.25 milliseconds.

10. The decoding method of claim 1, further comprising:

clearing the setting of the flag at the end of the second period when the flag is set to the jitter status.

11. A signal processing circuit for receiving a modulation data carried by a coil signal and decoding the modulation data, the signal processing circuit comprising:

at least one comparator module, for receiving the coil signal and determining a jitter in the coil signal; and

a processor, coupled to the comparator module, configured to perform the following steps;

obtaining a trigger gap when the jitter appears in a peak location of a plurality of peaks in the coil signal;

determining a length of the trigger gap, and outputting a gap indicating signal when the length of the trigger gap is within a predefined range;

determining whether a plurality of gap indicating signals appear in a first period, and determining whether the plurality of gap indicating signals are scattered in the first period;

setting a flag to a jitter status according to determination results of whether the plurality of gap indicating signals appear in the first period and whether the plurality of gap indicating signals are scattered in the first period;

determining whether the flag is set to the jitter status during a second period, and accordingly filling a value in a time slot corresponding to the second period among a plurality of time slots for determining the modulation data; and

obtaining a data code of the modulation data according to a plurality of values filled in the plurality of time slots.

12. The signal processing circuit of claim 11, wherein the comparator module comprises a first comparator module and a second comparator module, wherein the first comparator module, the second comparator module and the processor perform the following steps to receive the coil signal and determine the jitter of the coil signal in order to obtain the trigger gap when the jitter appears in the peak location of the plurality of peaks in the coil signal:

setting, by the processor, a peak voltage level, allowing the first comparator module to track peak voltages of the plurality of peaks;

decreasing, by the processor, the peak voltage level by a predetermined value to obtain a determination voltage level;

comparing, by the second comparator module, the determination voltage level with the coil signal; and

determining, by the processor, the trigger gap appears when the second comparator module detects that the peak voltage of a peak among the plurality of peaks is smaller than the determination voltage level.

13. The signal processing circuit of claim 11, wherein the first period is divided into a first sub-period and a second sub-period, and the processor performs the following steps to determine whether the plurality of gap indicating signals are scattered in the first period:

determining whether at least one of the plurality of gap indicating signals appears in the first sub-period;

determining whether at least one of the plurality of gap indicating signals appears in the second sub-period; and

determining that the plurality of gap indicating signals are scattered in the first period when the plurality of gap indicating signals appear in both of the first sub-period and the second sub-period.

14. The signal processing circuit of claim 11, wherein the processor perform the following step to set the flag to the jitter status according to the determination results of whether the plurality of gap indicating signals appear in the first period and whether the plurality of gap indicating signals are scattered in the first period:

setting the flag to the jitter status when the gap indicating signals appear in the first period and the gap indicating signals are scattered in the first period.

15. The signal processing circuit of claim 11, wherein the processor performs the following steps to determine whether the flag is set to the jitter status during the second period and accordingly fill the value in the time slot corresponding to the second period among the plurality of time slots for determining the modulation data:

filling a first value in the time slot corresponding to the second period when the flag is set to the jitter status; and

filling a second value in the time slot corresponding to the second period when the flag is not set to the jitter status.

16. The signal processing circuit of claim 15, wherein the processor performs the following steps to obtain the data code of the modulation data according to the plurality of values filled in the plurality of time slots:

fetching a first time slot filled with the first value and a second time slot filled with the next first value among the plurality of time slots;

calculating an gap between the first time slot and the second time slot to determine whether the gap complies with a bit length of the data code; and

obtaining the data code according to a length of the gap.

17. The signal processing circuit of claim 16, wherein the processor is further configured to perform the following step:

determining at least one of a start bit and a parity check code of the modulation data according to the gap.

18. The signal processing circuit of claim 17, wherein the processor is further configured to perform the following step:

obtaining the start bit, a byte of data codes and the parity check code of the modulation data during a third period.

19. The signal processing circuit of claim 18, wherein the third period is equal to 50 milliseconds and the second period is equal to 0.25 milliseconds.

20. The signal processing circuit of claim 11, wherein the processor further performs the following step:

clearing the setting of the flag at the end of the second period when the flag is set to the jitter status.