Adaptable forward error correction

• US 10,574,391 B2
• Filed: 08/03/2017
• Issued: 02/25/2020
• Est. Priority Date: 08/03/2017
• Status: Expired due to Fees

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Inventors: Schmidtke, Hans-Juergen, Lyubomirsky, Ilya
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Alshack, Osman M
• Application Number:
  US15/668,634
• Publication Number:
  US 20190044654A1
• Time in Patent Office: 936 Days
• Field of Search: 714752, 714755, 714776
• CPC Class Codes: H04B 10/07953 Monitoring or measuring OSNR, BER or Q
• CPC Class Codes: H04B 10/516 Details of coding or modulation
• CPC Class Codes: H04L 1/0007 by modifying the frame length
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER

Abstract

Optical fiber data communications are described. An error correction circuit can receive a signal and correct bit errors of that signal. The circuit can then determine characteristics of the signal (e.g., its bit error rate (BER)) and adjust the operations performed to correct the bit errors of the signal based on the characteristics.

Claims

1. An optical fiber data communications system, comprising:

a first forward error correction (FEC) circuit configured to;

receive a first signal,

determine first characteristics representative of a quality of the first signal, and

change first operational parameters including by changing a first number of decoding iterations of the first FEC circuit to represent a first adjusted power consumption and a first desired performance level of the first FEC circuit based on the determined first characteristics representative of the quality of the first signal, wherein the first FEC circuit is configured to change the first operational parameters including by being configured to select a first block size representing a first number of bits to be analyzed at a time to correct bit errors; and

a second FEC circuit configured to;

receive a second signal,

determine second characteristics representative of a quality of the second signal, and

change second operational parameters including by changing a second number of decoding iterations of the second FEC circuit to represent a second adjusted power consumption and a second desired performance level of the second FEC circuit based on the determined second characteristics representative of a quality of the second signal, wherein the second FEC circuit is configured to change the second operational parameters including by being configured to select a second block size representing a second number of bits to be analyzed at a time to correct bit errors, the first block size and the second block size being different sizes;

wherein the first characteristics and the second characteristics being different, and the first desired performance level and the second desired performance level being different; and

wherein the first FEC circuit and the second FEC circuit are included on a same integrated circuit chip configured to independently control at least the different numbers of decoding iterations of the different FEC circuits on the same integrated circuit chip to optimize power consumption of at least one of the first FEC circuit or the second FEC circuit to have a lower power requirement.

2. The optical fiber data communications system of claim 1, wherein the first FEC circuit implements Reed-Solomon error correction, and the second FEC circuit also implements Reed-Solomon error correction.

3. The optical fiber data communications system of claim 1, wherein the first operational parameters includes the first number of decoding iterations to correct bit errors of the first signal, and the second operational parameters includes the second number of decoding iterations to correct bit errors of the second signal, the first number and the second number being different numbers.

4. The optical fiber data communications system of claim 1, wherein the first characteristics includes a bit error rate (BER) of the first signal, and the second characteristics includes a BER of the second signal.

5. The optical fiber data communications system of claim 4, wherein the BER of the first signal is different than the BER of the second signal, and the first operational parameters and the second operational parameters are different based on the BER of the first signal being different than the BER of the second signal.

6. The optical fiber data communications system of claim 4, wherein the BER of the first signal is higher than the BER of the second signal, and the first operational parameters are representative of the first FEC circuit performing more decoding iterations to correct bit errors than the second FEC circuit.

7. The optical fiber data communications system of claim 4, wherein the BER of the first signal is higher than the BER of the second signal, and the first operational parameters are representative of the first FEC circuit providing a higher coding gain than the second FEC circuit.

8. The optical fiber data communications system of claim 1, wherein the first characteristics includes a signal-to-noise ratio (SNR) of the first signal, and the second characteristics includes a SNR of the second signal.

9. The optical fiber data communications system of claim 8, wherein the SNR of the first signal is different than the SNR of the second signal.

10. A method, comprising:

receiving a first signal;

determining first characteristics representative of a quality of the first signal;

changing first operational parameters including by changing a first number of decoding iterations of a first forward error correction (FEC) circuit to represent a first adjusted power consumption and a first desired performance level of a first forward error correction based on the determined first characteristics representative of the quality of the first signal, wherein changing the first operational parameters includes selecting a first block size representing a first number of bits to be analyzed at a time to correct bit errors;

receiving a second signal;

determining second characteristics representative of a quality of the second signal; and

changing second operational parameters including by changing a second number of decoding iterations of a second FEC circuit to represent a second adjusted power consumption and a second desired performance level of a second forward error correction based on the determined second characteristics representative of a quality of the second signal, wherein changing the second operational parameters includes selecting a second block size representing a second number of bits to be analyzed at a time to correct bit errors, the first block size and the second block size being different sizes;

wherein the first characteristics and the second characteristics being different, and the first desired performance level and the second desired performance level being different; and

wherein the first FEC circuit and the second FEC circuit are included on a same integrated circuit chip configured to independently control at least the different numbers of decoding iterations of the different FEC circuits on the same integrated circuit chip to optimize power consumption of at least one of the first FEC circuit or the second FEC circuit to have a lower power requirement.

11. The method of claim 10, wherein the first forward error correction implements Reed-Solomon error correction, and the second forward error correction also implements Reed-Solomon error correction.

12. The method claim 10, wherein the first operational parameters includes the first number of decoding iterations to correct bit errors of the first signal, and the second operational parameters includes the second number of decoding iterations to correct bit errors of the second signal, the first number and the second number being different numbers.

13. The method of claim 10, wherein the first characteristics includes a bit error rate (BER) of the first signal, and the second characteristics includes a BER of the second signal.

14. The method of claim 13, wherein the BER of the first signal is different than the BER of the second signal, and the first operational parameters and the second operational parameters are different based on the BER of the first signal being different than the BER of the second signal.

15. The method of claim 13, wherein the BER of the first signal is higher than the BER of the second signal, and the first operational parameters are representative of the first forward error correction performing more decoding iterations to correct bit errors than the second forward error correction.

16. The method of claim 13, wherein the BER of the first signal is higher than the BER of the second signal, and the first operational parameters are representative of the first forward error correction providing a higher coding gain than the second forward error correction.

17. The method of claim 10, wherein the first characteristics includes a signal-to-noise ratio (SNR) of the first signal, and the second characteristics includes a SNR of the second signal.

18. A system, comprising:

a first forward error correction (FEC) circuit configured to;

receive a first signal,

determine first characteristics representative of a quality of the first signal, and

determine first operational parameters including by determining a first number of decoding iterations of the first FEC circuit to represent a first power consumption and a first desired performance level of the first FEC circuit based on the determined first characteristics representative of the quality of the first signal, wherein the first FEC circuit is configured to determine the first operational parameters including by being configured to select a first block size representing a first number of bits to be analyzed at a time to correct bit errors; and

a second FEC circuit configured to;

receive a second signal,

determine second characteristics representative of a quality of the second signal, and

determine second operational parameters including by determining a second number of decoding iterations of the second FEC circuit to represent a second power consumption and a second desired performance level of the second FEC circuit based on the determined second characteristics representative of a quality of the second signal, wherein the second FEC circuit is configured to determine the second operational parameters including by being configured to select a second block size representing a second number of bits to be analyzed at a time to correct bit errors, the first block size and the second block size being different sizes;

wherein the first characteristics and the second characteristics being different, and the first desired performance level and the second desired performance level being different; and

wherein the first FEC circuit and the second FEC circuit are included on a same integrated circuit chip configured to independently control at least the different numbers of decoding iterations of the different FEC circuits on the same integrated circuit chip to optimize power consumption of at least one of the first FEC circuit or the second FEC circuit to have a lower power requirement.

19. The system of claim 18, wherein the first FEC circuit implements Reed-Solomon error correction, and the second FEC circuit also implements Reed-Solomon error correction.

20. The system of claim 18, wherein the first operational parameters includes the first number of decoding iterations to correct bit errors of the first signal, and the second operational parameters includes the second number of decoding iterations to correct bit errors of the second signal, the first number and the second number being different numbers.