Core testing machine

• US 10,578,670 B2
• Filed: 10/02/2017
• Issued: 03/03/2020
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: Contec LLC (Contec LLC /Management/)
• Original Assignee: Contec LLC (Contec LLC /Management/)
• Inventors: Kumar, Samant, Kumar, Dinesh, Diddimani, Shivashankar, Samaiya, Gunjan
• Primary Examiner(s): Patel, Kamini B
• Application Number:
  US15/722,235
• Publication Number:
  US 20180024193A1
• Time in Patent Office: 883 Days
• Field of Search: 714 27
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence

Abstract

A testing system includes a slot configured to receive a device-under-test (DUT), and a core testing processor configured to communicate with a user interface and with the slot, wherein the core testing processor is associated with communication that is independent of any other communications transmitted within the system, and wherein the core testing processor executes a set of tests associated with the DUT.

Claims

1. A core testing processor configured to

receive serial number information for a plurality of devices under test (DUTs);

retrieve, from a source selected from a database and a web service, type information comprising a make or model of each DUT, retrieval of the type information based upon the serial number information;

load test configuration information specific to each type of DUT;

read a test step of the test configuration information loaded for each DUT;

execute the test step read for each DUT;

determine whether each DUT passed or failed the executed test step;

responsive to a determination that a DUT passed the executed test step, determine whether, for each DUT that passed the executed test step, the loaded test configuration information contains a next test step to be executed;

responsive to a determination that the loaded test configuration contains a next test step to be executed, perform repeated tasks for each DUT for which a next test step exists, the repeated tasks comprising reading the test step, executing the test step read for each DUT, determining whether each DUT passed the executed test step, and determining whether, for each DUT that passed the executed test step, the loaded test configuration information contains a next step to be executed; and

responsive to a determination that the loaded test configuration does not contain a next test step to be executed, terminate the repeating step for each DUT for which a next test step does not exist.

2. The core testing processor of claim 1, further configured to

responsive to a determination that a DUT failed the executed test step, determine whether to abort testing for each DUT that failed the executed test step;

and

responsive to a determination to not abort testing, perform the repeated tasks until reaching the determination that the loaded test configuration does not contain a next test step to be executed.

3. The core testing processor of claim 2, further configured to, responsive to a determination to abort testing, indicate testing failure for each DUT for which a determination to abort testing has been made.

4. The core testing processor of claim 2, further configured to communicate, upon completion of each test step, results of the completed test step to a user.

5. The core testing processor of claim 4, wherein communicating the results of the completed test step to the user comprises sending a message to a browser of the user via web-sockets.

6. A system for testing devices, comprising:

the core testing processor of claim 1; and

a slot configured to receive a device-under-test (DUT), the slot communicating with the core testing processor and with a lightweight virtualization container configured for association with an interface of a DUT receivable in the slot, the lightweight virtualization container enabling isolation of testing processes and testing resources associated with the DUT receivable in the slot.

7. The system for testing devises of claim 6, where in the core testing processor is configured to communicate with a user interface and with the slot, wherein the core testing processor is associated with communication that is independent of other communications transmitted within the system.

8. The system for testing devices of claim 7, wherein the core testing processor is associated with a web socket for communication that is independent of other communications transmitted within the system.