Co-packaging photonic integrated circuits and application specific integrated circuits

• US 10,578,799 B2
• Filed: 01/12/2018
• Issued: 03/03/2020
• Est. Priority Date: 04/26/2012
• Status: Active Grant

• Current Assignee: Acacia Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Acacia Communications Incorporated (Cisco Systems, Inc.)
• Inventors: Doerr, Christopher, Swanson, Eric, Vermeulen, Diedrik, Azemati, Saeid, Stahl, Jon
• Primary Examiner(s): Kianni, Kaveh C
• Assistant Examiner(s): Lam, Hung Q
• Application Number:
  US15/870,468
• Publication Number:
  US 20180203187A1
• Time in Patent Office: 781 Days
• Field of Search: 385 14, 385 15, 385 37, 2502141
• CPC Class Codes: G02B 6/12 of the integrated circuit kind electric integrated circuits H01L27/00
• CPC Class Codes: G02B 6/4269 with heat sinks or radiation fins
• CPC Class Codes: G02B 6/428 containing printed circuit boards [PCB]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

Disclosed herein are designs, structures and techniques for advanced packaging of multi-function photonic integrated circuits that allow such high-performance multi-function photonic integrated circuits to be co-packaged with a high-performance multi-function ASIC thereby significantly reducing strenuous interconnect challenges and lowering costs, power and size of the overall devices.

Claims

1. A co-packaging arrangement comprising:

a photonic integrated circuit (PIC) and an application specific integrated circuit (ASIC), wherein the PIC and the ASIC are disposed on a substrate within a housing;

wherein said PIC is coupled to at least two optical fibers that couple light between structures outside the housing to optical waveguides on the PIC,

wherein said PIC includes one or more optical modulators and one or more optical detectors and said substrate includes electrical interconnects for interconnecting the PIC to the ASIC; and

wherein the one or more optical modulators are driven directly from a digital-to-analog converter (DAC) that is located on the ASIC.

2. The arrangement of claim 1, wherein said PIC includes at least one surface grating coupler.

3. The arrangement of claim 1, wherein a transimpedance amplifier (TIA), electrically coupled to the one or more optical detectors, is located on the ASIC with no active electrical elements in-between the one or more optical detectors and the TIA.

4. The arrangement of claim 1, wherein the PIC includes a number of high-speed Input/Output connectors positioned along one single edge of the PIC.

5. The arrangement of claim 1, wherein the housing includes a heat sink overlying a top of the housing, wherein the housing includes an opening through which the at least two optical fibers pass.

6. The arrangement of claim 1, wherein the housing includes a window through which light is coupled to the PIC.

7. The arrangement of claim 1, wherein the ASIC is flip-chip mounted and die bonded to the substrate.

8. The arrangement of claim 1, wherein the one or more optical modulators and the one or more optical detectors form part of a coherent transceiver.

9. The arrangement of claim 1, wherein the PIC is coupled to the substrate through die bonds, and wherein the die bonds are connected to through silicon vias (TSVs) disposed within the PIC.

10. The arrangement of claim 1, wherein the PIC is edge-coupled to the at least two optical fibers.

11. The arrangement of claim 1, wherein there are no electronic amplifiers electrically connected between the one or more optical modulators and the DAC.

12. A co-packaging arrangement comprising:

a photonic integrated circuit (PIC) and an application specific integrated circuit (ASIC), wherein the PIC and the ASIC are disposed on a substrate within a housing;

wherein the PIC comprises a transceiver having one or more optical modulators driven directly from a digital-to-analog converter (DAC) that is located on the ASIC;

wherein the PIC is coupled to at least two optical fibers that couple light between structures outside the housing to optical waveguides on the PIC; and

a tunable laser disposed outside of the housing, such that there are no cooling devices within the housing.

13. The arrangement of claim 12, wherein the transceiver is a coherent transceiver.

14. The arrangement of claim 12, wherein the ASIC is disposed on the substrate beside the PIC.

15. The arrangement of claim 12, wherein the transceiver further comprises one or more optical detectors, and the ASIC comprises a transimpedance amplifier (TIA) electrically coupled to the one or more optical detectors, wherein there are no active electrical elements in-between the one or more optical detectors and the TIA.

16. The arrangement of claim 12, wherein the PIC comprises a number of high-speed Input/Output connectors positioned along one single edge of the PIC.

17. The arrangement of claim 12, wherein the housing comprises a heat sink overlying a top surface of the housing, wherein the housing includes an opening through which the at least two optical fibers pass.

18. The arrangement of claim 12, wherein the PIC is coupled to the substrate through die bonds, and wherein the die bonds are connected to through silicon vias (TSVs) disposed within the PIC.

19. The arrangement of claim 12, wherein the arrangement further comprises a v-groove assembly, wherein one of the at least two optical fibers is disposed, at least in part, on a v-groove of the v-groove assembly.

20. The arrangement of claim 12, wherein there are no electronic amplifiers electrically connected between the one or more optical modulators and the DAC.