Method and apparatus for securing communication of instructions to manage antenna power output

• US 10,579,117 B2
• Filed: 02/18/2019
• Issued: 03/03/2020
• Est. Priority Date: 08/02/2017
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Bologna, Benny J., Koshy, Kamal J., Montero, Adolfo S.
• Primary Examiner(s): Nguyen, Linh V
• Application Number:
  US16/278,641
• Publication Number:
  US 20190179385A1
• Time in Patent Office: 379 Days
• Field of Search: 343714
• CPC Class Codes: G05B 15/02 electric
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: H01Q 1/243 with built-in antennas
• CPC Class Codes: H01Q 1/245 with means for shaping the antenna pattern, e.g. in order to protect user against rf exposure
• CPC Class Codes: H01Q 21/28 Combinations of substantially independent non-interacting antenna units or systems multiple beam H01Q25/00
• CPC Class Codes: H04B 2203/5441 Wireless systems or telephone
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 2012/2843 Mains power line
• CPC Class Codes: H04L 41/0661 by reconfiguring faulty entities
• CPC Class Codes: H04L 41/0663 Performing the actions predefined by failover planning, e.g. switching to standby network elements
• CPC Class Codes: H04L 49/557 Error correction, e.g. fault recovery or fault tolerance
• CPC Class Codes: H04W 84/12 WLAN [Wireless Local Area Networks]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and an information handling system comprising a processor executing instructions of a basic input/output system (BIOS) module operatively connected to a network interface device standard absorption rate (SAR) antenna power control register via a bus interface and the processor executing code instructions for a power management command for altering a power level of a transmission by an operably connected transmitting antenna according to SAR requirements in response to detection at a sensor indicating a change to transmission power levels is required, where the bus interface is secured by implementing a challenge/response cryptographic system between the BIOS module and the network interface device before allowing the read/write command to access the standard absorption rate control register.

Claims

1. An information handling system comprising:

a processor executing instructions of a basic input/output system (BIOS) module operatively connected to a network interface device standard absorption rate (SAR) antenna power control register via a peripheral component interconnect express electronic (PCIe) bus interface;

the processor executing code instructions for a read/write command for altering a power level of a transmission by an operably connected transmitting antenna according to SAR requirements in response to detection at a sensor indicating a change to transmission power levels is required; and

the PCIe bus interface secured by implementing a challenge/response cryptographic system between the BIOS module and the network interface device before allowing the read/write command to access the standard absorption rate control register at the network interface device, wherein the BIOS module and the network interface device may each access a copy of a secret key.

2. The information handling system of claim 1 further comprising:

the processor executing code instructions of the challenge/response cryptographic system to ignore attempts of the BIOS module to transmit the read/write command via the secured PCIe bus interface if the challenge/response cryptographic system does not yield a first response value matching a second response value.

3. The information handling system of claim 1 further comprising:

the processor executing code instructions of the BIOS module to receive the read/write command instruction to decrease a voltage supplied to the transmitting antenna in response to a change in capacitance sensed across a proximity sensing element.

4. The information handling system of claim 3 further comprising:

the BIOS module to transmit the read/write command to the standard absorption rate control register at the network interface device within the preset time period.

5. The information handling system of claim 1, wherein a first response value and a second response value are determined by the challenge/response cryptographic system based on a randomly generated number using an asymmetric cryptographic method.

6. The information handling system of claim 1, wherein a first response value and a second response value are determined by the challenge/response cryptographic system based on a randomly generated number using an elliptic curve cryptographic method.

7. The information handling system of claim 1, wherein a challenge register and a response register of a memory accessible by the challenge/response cryptographic system allow for storage of data records having a length of bits at a protocol-acceptable secure level.

8. A method of securing communication bus transmissions controlling antenna power output comprising:

executing instructions, via a processor, of a basic input/output system (BIOS) module to prepare a power management command for altering a transmission power level of an operably connected transmitting antenna according to SAR requirements in response to detection at a sensor indicating a change to transmission power levels is required;

implementing a challenge/response cryptographic system between the BIOS module and the network interface device, wherein the BIOS module and the network interface device may each access a copy of a secret key to secure a bus interface between the BIOS module and the network interface device; and

transmitting, via the secured bus interface, the read/write command to a standard absorption rate control register at the network interface device.

9. The method of claim 8 further comprising:

ignoring attempts of the processor to transmit the power management command via the secure bus interface if a first response value does not match a second response value generated via the challenge/response cryptographic system.

10. The method of claim 8 further comprising:

executing the power management command stored in the standard absorption rate control register to alter transmission power level of the transmitting antenna.

11. The method of claim 10 further comprising:

receiving the power management command to alter a voltage supplied to the transmitting antenna in response to a change in capacitance sensed across a proximity sensing element from an operably connected integrated circuit.

12. The method of claim 8, wherein a first response value and a second response value are determined by the challenge/response cryptographic system based on a randomly generated challenge value using an asymmetric cryptographic method.

13. The method of claim 8, wherein the power management command includes a command to decrease the voltage supplied to the transmitting antenna.

14. The method of claim 8, wherein the bus interface is a PCIe bus interface.

15. An information handling system comprising:

a PCIe bus interface operatively connecting a basic input/output system (BIOS) module at a processor to a network interface device;

standard absorption rate (SAR) antenna power control register via a bus interface;

the processor executing code instructions for the BIOS module to issue a power management command in response to detection at a sensor indicating a change to transmission power levels;

a challenge/response cryptographic system implemented between the BIOS module and the network interface device wherein the BIOS module and the network interface device may each access a copy of a secret key to generate response values in a challenge register and a response register to secure the bus interface; and

transmitting the power management command, via the secured bus interface, to a standard absorption rate control register at the network interface device for execution to alter transmitting power of an operatively connected antenna.

16. The information handling system of claim 15 further comprising:

the processor executing code instructions of the challenge/response cryptographic system to ignore attempts of the BIOS module to transmit the power management command via the secure bus interface if a first response value does not match a second response value.

17. The information handling system of claim 15 further comprising:

the processor executing code instructions of the BIOS module to receive the power management command to decrease a voltage supplied to the transmitting antenna in response to a change in capacitance sensed across a proximity sensing element.

18. The information handling system of claim 15 further comprising:

the processor executing code instructions to store the power management command in the standard absorption rate control register; and

execute the power management command for the operatively connected antenna.

19. The information handling system of claim 15, wherein a first response value in a challenge register and a second response value in a response register are determined based on randomly generated numbers using an elliptic curve cryptographic method.

20. The information handling system of claim 15, wherein the secure bus interface is a PCIe bus interface.