Apparatus and method for applying suitable voltage to a component of a system-on-chip

• US 10,579,131 B2
• Filed: 11/16/2017
• Issued: 03/03/2020
• Est. Priority Date: 11/16/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jaecheol, Kim, Jinkyu, Kim, Dongwoo, Kim, Jeongho, Chaung, Jaesoo, Ha, Jongshik, Oh, Heetae, Yu, Hyeokseon, Lee, Seungyoung, Choi, Wooyoung, Han, Jaewoong, Hur, Mangun
• Primary Examiner(s): Patel, Nitin C
• Application Number:
  US15/814,790
• Publication Number:
  US 20180136713A1
• Time in Patent Office: 838 Days
• Field of Search: None
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 15/7807 System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
• CPC Class Codes: H03F 3/2173 of the bridge type
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An electronic device includes a system-on-chip (SoC) including at least one component, a memory, and a processor functionally connected to the SoC and the memory. The processor is configured to apply a default voltage for driving the at least one component at a specific frequency. The processor is also configured to determine whether data on an offset voltage corresponding to the at least one component and the specific frequency is stored. The processor is further configured to apply the offset voltage, being different from the default voltage, to the at least one component when the data on the offset voltage is stored. Other embodiments are possible.

Claims

1. An electronic device comprising:

a system-on-chip (SoC) including at least one component;

a memory; and

a processor functionally connected to the SoC and the memory, wherein the processor is configured to;

apply a default voltage for driving the at least one component at a specific frequency,

determine whether data on an offset voltage corresponding to the at least one component and the specific frequency is stored in an offset voltage table,

apply the offset voltage, being different from the default voltage, to the at least one component when the data on the offset voltage is stored,

acquire data on the offset voltage by using a hardware performance monitor (HPM) when the data on the offset voltage is not stored, and

update the offset voltage table based on the acquired data.

2. The electronic device of claim 1, wherein when applying the default voltage, the processor is further configured to:

load a dynamic voltage and frequency scaling (DVFS) table, and

apply the default voltage by identifying the default voltage corresponding to the at least one component and the specific frequency in the DVFS table.

3. The electronic device of claim 1, wherein the at least one component includes at least one of a central processing unit (CPU), an internal (INT) memory, a memory interface (MIF) memory, a graphics processing unit (GPU), and an image signal processor (ISP).

4. The electronic device of claim 1, wherein the processor is further configured to:

verify the acquired data on the offset voltage, and

store the verified data on the offset voltage in the offset voltage table.

5. The electronic device of claim 4, wherein when acquiring the data on the offset voltage, the processor is further configured to:

acquire information about the default voltage and an HPM value corresponding to the at least one component and the specific frequency, and

acquire the data on the offset voltage corresponding to the default voltage and the HPM value.

6. The electronic device of claim 5, wherein when acquiring the data on the offset voltage, the processor is further configured to:

acquire the data on the offset voltage from an updated default voltage obtained by decreasing the default voltage by a predetermined rate.

7. The electronic device of claim 6, wherein the predetermined rate is a margin value that is set by a vender manufacturing the SoC.

8. The electronic device of claim 6, wherein when acquiring the data on the offset voltage, the processor is further configured to:

compare the HPM value in a condition where the SoC is manufactured with the HPM value in a condition where the SoC is mounted in the electronic device, and

acquire the data on the offset voltage, at least based on a difference between the compared HPM values.

9. The electronic device of claim 8, wherein when acquiring the data on the offset voltage, the processor is further configured to:

acquire the data on the offset voltage by subtracting a voltage corresponding to the difference between the compared HPM values from the updated default voltage when the HPM value in a condition where the SoC is mounted in the electronic device is greater than the HPM value in a condition where the SoC is manufactured, and

acquire the data on the offset voltage by adding a voltage corresponding to the difference between the compared HPM values to the updated default voltage when the HPM value in a condition where the SoC is mounted in the electronic device is smaller than the HPM value in a condition where the SoC is manufactured.

10. The electronic device of claim 1, wherein when applying the offset voltage to the at least one component, the processor is further configured to:

identify an operating mode of the electronic device, and

apply a particular voltage to the at least one component, the particular voltage being obtained by lowering a predetermined rate of a difference between the default voltage and the offset voltage from the default voltage, based on the identified operating mode.

11. A method for driving an electronic device that includes a system-on-chip (SoC) and at least one component, the method comprising:

applying a default voltage for driving the at least one component at a specific frequency;

determining whether data on an offset voltage corresponding to the at least one component and the specific frequency is stored in an offset voltage table;

applying the offset voltage, being different from the default voltage, to the at least one component when the data on the offset voltage is stored;

acquiring data on the offset voltage by using a hardware performance monitor (HPM) when the data on the offset voltage is not stored; and

updating the offset voltage table based on the acquired data.

12. The method of claim 11, wherein applying the default voltage comprises:

loading a dynamic voltage and frequency scaling (DVFS) table, and

applying the default voltage by identifying the default voltage corresponding to the at least one component and the specific frequency in the DVFS table.

13. The method of claim 11, wherein the at least one component includes at least one of a central processing unit (CPU), an internal (INT) memory, a memory interface (MIF) memory, a graphics processing unit (GPU), and an image signal processor (ISP).

14. The method of claim 12, further comprising:

verifying the acquired data on the offset voltage; and

updating the offset voltage table comprises storing the verified data on the offset voltage in the offset voltage table.

15. The method of claim 14, wherein acquiring the data on the offset voltage comprises:

acquiring information about the default voltage and an HPM value corresponding to the at least one component and the specific frequency, and

acquiring the data on the offset voltage corresponding to the default voltage and the HPM value.

16. The method of claim 15, wherein acquiring the data on the offset voltage comprises:

acquiring the data on the offset voltage from an updated default voltage obtained by decreasing the default voltage by a predetermined rate.

17. The method of claim 16, wherein the predetermined rate is a margin value is set by a vender manufacturing the SoC.

18. The method of claim 16, wherein acquiring the data on the offset voltage comprises:

comparing the HPM value in a condition where the SoC is manufactured with the HPM value in a condition where the SoC is mounted in the electronic device, and

acquiring the data on the offset voltage, at least based on a difference between the compared HPM values.

19. The method of claim 18, further comprising:

acquiring the data on the offset voltage by subtracting a voltage corresponding to the difference between the compared HPM values from the updated default voltage when the HPM value in a condition where the SoC is mounted in the electronic device is greater than the HPM value in a condition where the SoC is manufactured, and

acquiring the data on the offset voltage by adding a voltage corresponding to the difference between the compared HPM values to the updated default voltage when the HPM value in a condition where the SoC is mounted in the electronic device is smaller than the HPM value in a condition where the SoC is manufactured.

20. The method of claim 11, wherein applying the offset voltage to the at least one component comprises:

identifying an operating mode of the electronic device, and

applying a particular voltage to the at least one component, the particular voltage being obtained by lowering a predetermined rate of a difference between the default voltage and the offset voltage from the default voltage, based on the identified operating mode.