Memory having a static cache and a dynamic cache

• US 10,579,537 B2
• Filed: 05/02/2019
• Issued: 03/03/2020
• Est. Priority Date: 06/10/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hale, Christopher S., Ratnam, Sampath K., Muchherla, Kishore K.
• Primary Examiner(s): Lane, John A
• Application Number:
  US16/401,382
• Publication Number:
  US 20190258584A1
• Time in Patent Office: 306 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: G06F 2212/281 Single cache
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.

Claims

1. An apparatus, comprising:

a memory having a first portion and a second portion; and

circuitry configured to;

operate the first portion of the memory as a static cache;

operate the second portion of the memory as a dynamic cache; and

adjust a size of the dynamic cache based on an amount of data stored in the memory by operating the dynamic cache as a single level cell cache or multilevel cell memory based on whether the entire first portion of the memory has data stored therein.

2. The apparatus of claim 1, wherein adjusting the size of the dynamic cache includes operating all of the dynamic cache as the single level cell cache.

3. The apparatus of claim 1, wherein adjusting the size of the dynamic cache includes operating none of the dynamic cache as the single level cell cache.

4. The apparatus of claim 3, wherein operating none of the dynamic cache as the single level cell cache includes operating the dynamic cache as the as multilevel cell memory.

5. The apparatus of claim 1, wherein:

the static cache is a static single level cell (SLC) cache.

6. A method of operating memory, comprising:

operating a first portion of a memory as a static cache;

operating a second portion of the memory as a dynamic cache; and

adjusting a size of the dynamic cache based on an amount of data stored in the memory by;

operating the dynamic cache as a single level cell cache when the entire first portion of the memory has data stored therein; and

operating the dynamic cache as multilevel cell memory when less than the entire first portion of the memory has data stored therein.

7. The method of claim 6, wherein adjusting the size of the dynamic cache includes:

operating all of the dynamic cache as the single level cell cache when the entire first portion of the memory has data stored therein; and

operating none of the dynamic cache as the single level cell cache when less than the entire first portion of the memory has data stored therein.

8. The method of claim 6, wherein the method includes operating the first portion of the memory as the static cache for an entire lifetime of the memory.

9. The method of claim 6, wherein the method includes operating a third portion of the memory as multilevel cell memory.

10. The method of claim 6, wherein the method includes:

receiving a command to program data to the memory; and

programming the data received in the command to the static cache or to the dynamic cache.

11. The method of claim 10, wherein the method includes determining which one of the static cache or the dynamic cache to program the data received in the command to based on whether the entire first portion of the memory has data stored therein.

12. An apparatus, comprising:

a memory having a first portion, a second portion, and a third portion; and

circuitry configured to;

operate the first portion of the memory as a static cache;

operate the second portion of the memory as a dynamic cache;

operate the third portion of the memory as multilevel cell (MLC) memory; and

adjust a size of the dynamic cache based on an amount of data stored in the memory by operating the dynamic cache as a single level cell (SLC) cache or MLC memory based on whether the entire first portion of the memory has data stored therein.

13. The apparatus of claim 12, wherein the memory includes dynamic random access memory (DRAM).

14. The apparatus of claim 12, wherein the MLC memory of the third portion of the memory comprises quadruple level memory.

15. The apparatus of claim 12, wherein the circuitry is configured to:

receive a command to program data to the memory; and

program the data received in the command to the static cache, the dynamic cache, or the MLC memory of the third portion of the memory.

16. The apparatus of claim 15, wherein the circuity is configured to determine which one of the static cache, the dynamic cache, or the MLC memory to program the data received in the command to based on whether the entire first portion of the memory has data stored therein.

17. The apparatus of claim 12, wherein the first portion of the memory is smaller than the second portion of the memory.

18. The apparatus of claim 12, wherein the first portion of the memory, the second portion of the memory, and the third portion of the memory each include a number of physical blocks of memory cells.