Systems and methods for generating stagger delays in memory devices
First Claim
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1. A semiconductor device, comprising:
- a plurality of memory banks;
an output buffer configured to couple to the plurality of memory banks;
a plurality of switches configured to couple a voltage source to the output buffer; and
a stagger delay circuit, comprising;
a resistor-capacitor (RC) circuit configured to output a current signal that corresponds to a data voltage signal received by the RC circuit; and
a logic circuit configured to;
determine a strength of the current signal; and
send a first gate signal to a first portion of the plurality of switches based on the strength, wherein the first gate signal is configured to cause each of the first portion of the plurality of switches to close.
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Abstract
A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.
11 Citations
20 Claims
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1. A semiconductor device, comprising:
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a plurality of memory banks; an output buffer configured to couple to the plurality of memory banks; a plurality of switches configured to couple a voltage source to the output buffer; and a stagger delay circuit, comprising; a resistor-capacitor (RC) circuit configured to output a current signal that corresponds to a data voltage signal received by the RC circuit; and a logic circuit configured to; determine a strength of the current signal; and send a first gate signal to a first portion of the plurality of switches based on the strength, wherein the first gate signal is configured to cause each of the first portion of the plurality of switches to close. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for controlling one or more operations of a semiconductor device, comprising:
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receiving, at a circuit, a current signal from a resistor-capacitor (RC) circuit, wherein the current signal corresponds to data received by the RC circuit; determining, at the circuit, a strength of the current signal; and transmitting, from the circuit, a first gate signal to a first set of switches within the semiconductor device based on the strength of the current signal, wherein the first gate signal is configured to cause the first set of switches to couple a voltage source to an output buffer, and wherein the output buffer is configured to couple to one or more memory banks. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A system comprising a processor for controlling one or more operations of a semiconductor device, wherein the processor is configured to:
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receive a current signal from a resistor-capacitor (RC) circuit, wherein the current signal corresponds to data received by the RC circuit; determine a strength of the current signal; and transmit a first gate signal to a first set of switches within the semiconductor device based on the strength of the current signal, wherein the first gate signal is configured to cause the first set of switches to couple a voltage source to an output buffer, and wherein the output buffer is configured to couple to one or more memory banks. - View Dependent Claims (17, 18, 19, 20)
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Specification