Memory device comprising electrically floating body transistor

• US 10,580,482 B2
• Filed: 09/27/2018
• Issued: 03/03/2020
• Est. Priority Date: 08/15/2014
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Berger, Neal, Widjaja, Yuniarto
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US16/144,544
• Publication Number:
  US 20190043554A1
• Time in Patent Office: 523 Days
• Field of Search: 36518907
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

Claims

1. A semiconductor memory instance comprising:

a plurality of memory sub-arrays, each said memory sub-array comprising;

a plurality of semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising;

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a buried well region contacting said floating body regions of said plurality of semiconductor cells, wherein said buried well region is common to said plurality of semiconductor memory cells in said memory sub-array; and

a first decoder circuit to select at least one of said at least one column or at least one of said at least one row; and

a second decoder circuit to select at least one of said memory sub-arrays.

2. The semiconductor memory instance of claim 1, wherein each said memory cell is configured to provide at least two stable states.

3. The semiconductor memory instance of claim 1, wherein each said memory cell further comprises a first region in electrical contact with said floating body region and a second region in electrical contact with said floating body region.

4. The semiconductor memory instance of claim 3, wherein each said memory cell further comprises a gate positioned between said first and second regions.

5. The semiconductor memory instance of claim 1, further comprising an address signal as an input to said second decoder circuit to select said buried well region.

6. The semiconductor memory instance of claim 1, wherein said second decoder circuit is configured to remove a bias to one or more of said buried well regions, while maintaining bias to others of said buried well regions.

7. The semiconductor memory instance of claim 1, further comprising a signal generator circuit to provide bias conditions for operations of said semiconductor memory instance.

8. The semiconductor memory instance of claim 7, wherein said signal generator circuit provides different ramp rates for read and write operations.

9. The semiconductor instance of claim 8, wherein said ramp rates for said read operations are lower than said ramp rates for said write operations.

10. The semiconductor instance of claim 1, comprising a fin structure extending from a substrate.