Three-dimensional one-time-programmable memory with a dummy word line

• US 10,580,507 B2
• Filed: 09/09/2018
• Issued: 03/03/2020
• Est. Priority Date: 04/14/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Lozada, Alfredo Bermudez
• Application Number:
  US16/125,713
• Publication Number:
  US 20180366206A1
• Time in Patent Office: 541 Days
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2216/12 Reading and writing aspects of erasable programmable read-only memories
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

To reduce the pre-programming cost, an efficient three-dimensional one-time-programmable read-only memory (3D-OTP) is disclosed. It comprises a dummy word line and a plurality of dummy bit lines. Only the dummy OTP cells at the intersections of the dummy word line and dummy bit lines are programmed. All other dummy OTP cells are unprogrammed.

Claims

1. A multi-bit-per-cell three-dimensional one-time-programmable read-only memory (3D-OTP), comprising:

a semiconductor substrate including transistors thereon;

an OTP array stacked above said semiconductor substrate, wherein said OTP array comprises a plurality of data word lines, a plurality of data bit lines and a plurality of data OTP cells, said data OTP cells having at least three states including an unprogrammed state, first and second programmed states, wherein the resistances of said data OTP cells in said first and second programmed states are different;

a dummy word line in parallel with said data word lines;

first and second dummy bit lines in parallel with said data bit lines;

first dummy OTP cell at the intersection of said dummy word line and said first dummy bit line, wherein said first dummy OTP cell is in said first programmed state;

second dummy OTP cell at the intersection of said dummy word line and said second dummy bit line, wherein said second dummy OTP cell is in said second programmed state;

wherein all dummy OTP cells at the intersections of said data word lines and said dummy bit line are unprogrammed; and

, all dummy OTP cells at the intersections of said dummy word line and said data bit lines are unprogrammed.

2. The 3D-OTP according to claim 1, further comprising:

a first differential amplifier coupled with said first dummy bit line; and

,

a second differential amplifier coupled with said second dummy bit line.