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Self-aligned single diffusion break for fully depleted silicon-on-insulator and method for producing the same

  • US 10,580,684 B2
  • Filed: 04/11/2018
  • Issued: 03/03/2020
  • Est. Priority Date: 04/11/2018
  • Status: Active Grant
First Claim
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1. A device comprising:

  • a buried oxide (BOX) layer over a silicon (Si) substrate;

    a silicon-on-insulator (SOI) layer over a portion of the BOX layer;

    a pair of gates over the SOI layer and laterally separated, each gate including a gate oxide layer over the SOI layer, a gate electrode layer over the gate oxide layer, an amorphous Si layer over the gate electrode layer, and a pair of first sidewall spacers;

    a dummy gate over a portion of the BOX layer with a u-shaped spacer liner and a spacer structure between a pair of second sidewall spacers, the dummy gate laterally separated from and situated in-between the pair of gates;

    a raised source/drain (S/D) epitaxial regions over the SOI layer between and adjacent to the pair of first sidewall spacers and the pair of second sidewall spacers;

    a silicide layer in a portion of each raised S/D epitaxial regions and the pair of gates;

    a third spacer over non-silicide portion of each raised S/D epitaxial regions and along a sidewall portion of the pair of first sidewall spacers and the pair of second sidewall spacers;

    a fourth spacer over and along sidewall portion of the third spacer;

    a barrier layer over the raised S/D epitaxial regions, the third spacer, the fourth spacer, the pair of gates and the dummy gate;

    a contact through the barrier layer down to the silicide layer between the dummy gate and each gate of the pair; and

    an interlayer dielectric (ILD) layer over the barrier layer and between and adjacent to the contacts, an upper surface of the ILD layer coplanar with the contacts.

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