Self-aligned single diffusion break for fully depleted silicon-on-insulator and method for producing the same
First Claim
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1. A device comprising:
- a buried oxide (BOX) layer over a silicon (Si) substrate;
a silicon-on-insulator (SOI) layer over a portion of the BOX layer;
a pair of gates over the SOI layer and laterally separated, each gate including a gate oxide layer over the SOI layer, a gate electrode layer over the gate oxide layer, an amorphous Si layer over the gate electrode layer, and a pair of first sidewall spacers;
a dummy gate over a portion of the BOX layer with a u-shaped spacer liner and a spacer structure between a pair of second sidewall spacers, the dummy gate laterally separated from and situated in-between the pair of gates;
a raised source/drain (S/D) epitaxial regions over the SOI layer between and adjacent to the pair of first sidewall spacers and the pair of second sidewall spacers;
a silicide layer in a portion of each raised S/D epitaxial regions and the pair of gates;
a third spacer over non-silicide portion of each raised S/D epitaxial regions and along a sidewall portion of the pair of first sidewall spacers and the pair of second sidewall spacers;
a fourth spacer over and along sidewall portion of the third spacer;
a barrier layer over the raised S/D epitaxial regions, the third spacer, the fourth spacer, the pair of gates and the dummy gate;
a contact through the barrier layer down to the silicide layer between the dummy gate and each gate of the pair; and
an interlayer dielectric (ILD) layer over the barrier layer and between and adjacent to the contacts, an upper surface of the ILD layer coplanar with the contacts.
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Abstract
A method of forming an SDB that is self-aligned to a dummy gate and the resulting device are provided. Embodiments include providing a plurality of gates over a SOI layer above a BOX layer, each gate having a pair of sidewall spacers and a cap layer, and a raised S/D epitaxial regions over the SOI layer between each gate; removing a gate of the plurality of gates and a portion of the SOI layer exposed by the removing of the gate, and a portion of the BOX layer underneath the SOI layer, the removing forms a trench; forming a liner of a first dielectric material over and along sidewalls of the trench; and filling the trench with a second dielectric material.
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Citations
7 Claims
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1. A device comprising:
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a buried oxide (BOX) layer over a silicon (Si) substrate; a silicon-on-insulator (SOI) layer over a portion of the BOX layer; a pair of gates over the SOI layer and laterally separated, each gate including a gate oxide layer over the SOI layer, a gate electrode layer over the gate oxide layer, an amorphous Si layer over the gate electrode layer, and a pair of first sidewall spacers; a dummy gate over a portion of the BOX layer with a u-shaped spacer liner and a spacer structure between a pair of second sidewall spacers, the dummy gate laterally separated from and situated in-between the pair of gates; a raised source/drain (S/D) epitaxial regions over the SOI layer between and adjacent to the pair of first sidewall spacers and the pair of second sidewall spacers; a silicide layer in a portion of each raised S/D epitaxial regions and the pair of gates; a third spacer over non-silicide portion of each raised S/D epitaxial regions and along a sidewall portion of the pair of first sidewall spacers and the pair of second sidewall spacers; a fourth spacer over and along sidewall portion of the third spacer; a barrier layer over the raised S/D epitaxial regions, the third spacer, the fourth spacer, the pair of gates and the dummy gate; a contact through the barrier layer down to the silicide layer between the dummy gate and each gate of the pair; and an interlayer dielectric (ILD) layer over the barrier layer and between and adjacent to the contacts, an upper surface of the ILD layer coplanar with the contacts. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification