Self-aligned single diffusion break for fully depleted silicon-on-insulator and method for producing the same

• US 10,580,684 B2
• Filed: 04/11/2018
• Issued: 03/03/2020
• Est. Priority Date: 04/11/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Wallner, Jin, Babich, Katherina, Singh, Sunil Kumar
• Primary Examiner(s): Chaudhari, Chandra
• Application Number:
  US15/950,907
• Publication Number:
  US 20190318955A1
• Time in Patent Office: 692 Days
• Field of Search: None
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method of forming an SDB that is self-aligned to a dummy gate and the resulting device are provided. Embodiments include providing a plurality of gates over a SOI layer above a BOX layer, each gate having a pair of sidewall spacers and a cap layer, and a raised S/D epitaxial regions over the SOI layer between each gate; removing a gate of the plurality of gates and a portion of the SOI layer exposed by the removing of the gate, and a portion of the BOX layer underneath the SOI layer, the removing forms a trench; forming a liner of a first dielectric material over and along sidewalls of the trench; and filling the trench with a second dielectric material.

Claims

1. A device comprising:

a buried oxide (BOX) layer over a silicon (Si) substrate;

a silicon-on-insulator (SOI) layer over a portion of the BOX layer;

a pair of gates over the SOI layer and laterally separated, each gate including a gate oxide layer over the SOI layer, a gate electrode layer over the gate oxide layer, an amorphous Si layer over the gate electrode layer, and a pair of first sidewall spacers;

a dummy gate over a portion of the BOX layer with a u-shaped spacer liner and a spacer structure between a pair of second sidewall spacers, the dummy gate laterally separated from and situated in-between the pair of gates;

a raised source/drain (S/D) epitaxial regions over the SOI layer between and adjacent to the pair of first sidewall spacers and the pair of second sidewall spacers;

a silicide layer in a portion of each raised S/D epitaxial regions and the pair of gates;

a third spacer over non-silicide portion of each raised S/D epitaxial regions and along a sidewall portion of the pair of first sidewall spacers and the pair of second sidewall spacers;

a fourth spacer over and along sidewall portion of the third spacer;

a barrier layer over the raised S/D epitaxial regions, the third spacer, the fourth spacer, the pair of gates and the dummy gate;

a contact through the barrier layer down to the silicide layer between the dummy gate and each gate of the pair; and

an interlayer dielectric (ILD) layer over the barrier layer and between and adjacent to the contacts, an upper surface of the ILD layer coplanar with the contacts.

2. The device according to claim 1, wherein a distance between the pair of second sidewall spacers of the dummy gate is equal to a distance between the pair of first sidewall spacers of the pair of gates neighboring the dummy gate.

3. The device according to claim 1, wherein the gate oxide layer comprises silicon dioxide (SiO₂), silicon oxynitride (SiON) or a metal oxide, and wherein the metal oxide comprises hafnium oxide (HfO₂), hafnium silicate (HfSiOx), hafnium nitride silicate (HfSiOxNy), zirconium dioxide (ZrO₂), titanium dioxide (TiO₂), aluminium oxide (Al₂O₃) or lanthanum oxide (La₂O₅).

4. The device according to claim 1, wherein the gate electrode layer comprises titanium nitride (TiN), aluminium (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), tantalum nitride (TaN), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), rhenium (Re) or ruthenium (Ru).

5. The device according to claim 1, wherein the u-shaped spacer liner and the pair of first sidewall spacers comprise oxide.

6. The device according to claim 1, wherein the spacer structure comprise nitride.

7. The device according to claim 1, wherein the raised S/D epitaxial region comprises silicon (Si), silicon germanium (SiGe), silicon carbide (SiC) or silicon-germanium-carbon (SiGeC).