Semiconductor memory device providing analysis and correcting of soft data fail in stacked chips
First Claim
1. A semiconductor memory device comprising:
- a first die group comprising at least one buffer die; and
a second die group comprising a plurality of memory dies, the plurality of memory dies stacked on the first die group, each of the memory dies included in the plurality of memory dies being configured to convey transmission data through at least one of a plurality of through silicon via (TSV) lines,wherein at least one of the plurality of memory dies includes a memory cell array including a data area and a parity area, and a first type error correction coding (ECC) circuit configured to correct a read error by performing error correction on read data from the memory cell array and generate corrected read data before the respective one of the at least one of the plurality of memory dies in which the first type ECC circuit is included conveys the corrected read data as the transmission data, and generate transmission parity bits based on the transmission data,wherein the at least one buffer die includes a second type ECC circuit configured tocorrect a transmission error to generate corrected transmission data using the transmission parity bits when the transmission error occurs in the transmission data received through the plurality of TSV lines if the transmission error is correctable, andgenerate information indicating a data error if the transmission error is not correctable, andwherein the at least one buffer die is configured totransmit the corrected transmission data if the transmission error is correctable, andtransmit the information indicating a data error if the transmission error is not correctable.
1 Assignment
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Accused Products
Abstract
The semiconductor memory device includes first group dies including at least one buffer die, and second group dies including a plurality of memory dies stacked on the first group dies and conveying data through a plurality of TSV lines. Here, at least one of the plurality of memory dies includes a first type ECC circuit which generates transmission parity bits using transmission data to be transmitted to the first group die, and the buffer die includes a second type ECC circuit which corrects, when a transmission error occurs in the transmission data received through the plurality of TSV lines, the transmission error using the transmission parity bits and generates error-corrected data.
27 Citations
16 Claims
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1. A semiconductor memory device comprising:
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a first die group comprising at least one buffer die; and a second die group comprising a plurality of memory dies, the plurality of memory dies stacked on the first die group, each of the memory dies included in the plurality of memory dies being configured to convey transmission data through at least one of a plurality of through silicon via (TSV) lines, wherein at least one of the plurality of memory dies includes a memory cell array including a data area and a parity area, and a first type error correction coding (ECC) circuit configured to correct a read error by performing error correction on read data from the memory cell array and generate corrected read data before the respective one of the at least one of the plurality of memory dies in which the first type ECC circuit is included conveys the corrected read data as the transmission data, and generate transmission parity bits based on the transmission data, wherein the at least one buffer die includes a second type ECC circuit configured to correct a transmission error to generate corrected transmission data using the transmission parity bits when the transmission error occurs in the transmission data received through the plurality of TSV lines if the transmission error is correctable, and generate information indicating a data error if the transmission error is not correctable, and wherein the at least one buffer die is configured to transmit the corrected transmission data if the transmission error is correctable, and transmit the information indicating a data error if the transmission error is not correctable. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor memory device comprising:
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a buffer die on a substrate; and a plurality of memory dies stacked on the buffer die and each of the plurality of memory dies being configured to transmit transmission data through at least one of a plurality of through silicon via (TSV) lines, wherein each of the plurality of memory dies includes a memory cell array including a data area and a parity area, and a first type error correction coding (ECC) circuit configured to correct a read error by performing error correction on read data from the memory cell array and generate the corrected read data before the respective one of the at least one of the plurality of memory dies in which the first type ECC circuit is included transmits the corrected read data as the transmission data, and generate transmission parity bits based on the transmission data, wherein the buffer die includes a second type ECC circuit configured to check whether a transmission error occurs in the transmission data received through the plurality of TSV lines correct the transmission error to generate corrected transmission data based on the transmission parity bits upon detecting the transmission error, if the transmission error is correctable, and generate information indicating a data error if the transmission error is not correctable, and wherein the buffer die is configured to transmit the corrected transmission data if the transmission error is correctable, and transmit the information indicating a data error if the transmission error is not correctable. - View Dependent Claims (10, 11, 12)
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13. A semiconductor memory device comprising:
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a first die group comprising at least one buffer die; and a second die group comprising a plurality of memory dies stacked on the first die group and each of the memory dies included in the plurality of memory dies being configured to convey transmission data through a plurality of through silicon via (TSV) lines, wherein at least one of the plurality of memory dies comprises a memory cell array including a data area and a parity area, and a cell core error correction coding (ECC) circuit configured to correct a read error by performing error correction on read data from the memory cell array and generate corrected read data before the respective one of the at least one of the plurality of memory dies in which the cell core ECC circuit is included conveys the corrected read data as the transmission data, and generate transmission parity bits based on the transmission data, and wherein at least one of the at least one buffer die comprises a via ECC circuit which is configured to correct, when a transmission error occurs in the transmission data received through the plurality of TSV lines, the transmission error using the transmission parity bits if the transmission error is correctable, generate error-corrected transmission data if the transmission error is correctable, send the error-corrected transmission data to a host if the transmission error is correctable, generate information indicating a data error if the transmission error is not correctable, and transmit the information indicating a data error if the transmission error is not correctable. - View Dependent Claims (14, 15, 16)
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Specification