Gate cut with integrated etch stop layer

• US 10,580,773 B2
• Filed: 08/03/2018
• Issued: 03/03/2020
• Est. Priority Date: 09/07/2016
• Status: Active Grant

• Current Assignee: Tessera LLC (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Bergendahl, Marc A., Greene, Andrew M., Venigalla, Rajasekhar
• Primary Examiner(s): Armand, Marc Anthony
• Application Number:
  US16/054,394
• Publication Number:
  US 20180342512A1
• Time in Patent Office: 578 Days
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Claims

1. A method of forming a power rail to semiconductor devices comprising:

providing a first active semiconductor region and a second active semiconductor region;

forming a gate structure extending from the first active region to the second active region having a gate cut trench separating the first active region from the second active region;

forming an etch stop layer in the gate cut trench; and

forming a power rail in the gate cut trench, wherein the conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

2. The method of claim 1, wherein the first active region comprises at least one first fin structure.

3. The method of claim 2, wherein the second active region comprises at least one second fin structure.

4. The method of claim 3, wherein the forming the gate structure extending from the first active region to the second active region comprises:

forming a dummy polysilicon gate structure over the channel portions of the at least one first fin structure, wherein first source and drain regions of the at least one first fin structure are present on opposing sides of the dummy polysilicon gate structure, and second source and drain regions of the at least one second fin structure are present on opposing sides of the dummy poly silicon gate structure; and

forming a gate sidewall spacer on the sidewalls of the gate structure.

5. The method of claim 1, wherein the gate cut region is formed using an anisotropic etch process.

6. The method of claim 1, wherein the gate cut trench is present through an interlevel dielectric layer extending between adjacent portions of the gate structure that have been separated by the gate cut trench.

7. The method of claim 1, wherein said forming the etch stop layer comprises depositing the etch stop layer on sidewalls of the gate cut trench.

8. The method of claim 7, wherein the etch stop layer is also formed on a base of the gate cut trench.

9. The method of claim 1, wherein forming a etch stop layer comprises hafnium oxide (HfO2).

10. The method of claim 9, further comprising forming a fill material atop the etch stop layer.

11. The method of claim 10, wherein the fill material is deposited to fill an entirety of the gate cut trench.

12. The method of claim 11, wherein the fill material is silicon nitride.

13. The method of claim 1, wherein said forming the power rail in the gate cut trench comprises:

forming an etch mask exposing a portion of the gate cut trench;

etching the fill material to provide a power rail opening, wherein the conformal etch stop layer obstructs lateral etching during said etching of the fill material to substantially eliminate power rail to gate structure shorting; and

depositing an electrically conductive material for the power rail in the power rail opening.

14. A method of forming a power rail to semiconductor devices comprising:

providing a first active semiconductor region and a second active semiconductor region;

forming a sacrificial gate structure extending from the first active region to the second active region having a gate cut trench separating the first active region from the second active region;

forming an etch stop layer in the gate cut trench;

substituting the sacrificial gate structure with a functional gate structure; and

forming a power rail in the gate cut trench.

15. The method of claim 14, wherein the sacrificial gate structure is composed of polysilicon.

16. The method of claim 14, wherein said forming the etch stop layer comprises depositing the etch stop layer on sidewalls of the gate cut trench and a base of the gate cut trench.

17. The method of claim 14, wherein forming an etch stop layer comprises hafnium oxide (HfO₂).

18. The method of claim 14, further comprising forming a fill material atop the etch stop layer.

19. The method of claim 18, wherein said forming the power rail in the gate cut trench comprises:

forming an etch mask exposing a portion of the gate cut trench;

etching the fill material to provide a power rail opening, wherein the conformal etch stop layer obstructs lateral etching during said etching of the fill material to substantially eliminate power rail to sacrificial gate structure shorting; and

depositing an electrically conductive material for the power rail in the power rail opening.

20. The method of claim 19, wherein said substituting the sacrificial gate structure with a functional gate structure comprises:

removing the sacrificial gate structure with a selective etch to provide a functional gate structure opening;

forming at least one gate dielectric in the functional gate structure opening; and

forming at least one gate conductor on the at least one gate dielectric in the functional gate structure opening.