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Gate cut with integrated etch stop layer

  • US 10,580,773 B2
  • Filed: 08/03/2018
  • Issued: 03/03/2020
  • Est. Priority Date: 09/07/2016
  • Status: Active Grant
First Claim
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1. A method of forming a power rail to semiconductor devices comprising:

  • providing a first active semiconductor region and a second active semiconductor region;

    forming a gate structure extending from the first active region to the second active region having a gate cut trench separating the first active region from the second active region;

    forming an etch stop layer in the gate cut trench; and

    forming a power rail in the gate cut trench, wherein the conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

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