Microelectronic devices including staircase structures, and related memory devices and electronic systems

• US 10,580,795 B1
• Filed: 08/15/2019
• Issued: 03/03/2020
• Est. Priority Date: 08/15/2019
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Luo, Shuangqiang, Chary, Indra V., Dorhout, Justin B.
• Primary Examiner(s): Schoenholtz, J. E.
• Application Number:
  US16/542,116
• Time in Patent Office: 201 Days
• Field of Search: None
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A microelectronic device comprises vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures; a staircase structure within the stack structure and having steps comprising edges of at least some of the tiers; a source tier underlying the stack structure and comprising: a source structure, and first discrete conductive structures horizontally separated from one another and the source structure by at least one dielectric material; conductive contact structures on the steps of the staircase structure; and first conductive pillar structures horizontally alternating with the conductive contact structures and vertically extending through the stack structure to the first discrete conductive structures of the source tier. A memory device, a 3D NAND Flash memory device, and an electronic system are also described.

Claims

1. A microelectronic device, comprising:

a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures;

a staircase structure within the stack structure and having steps comprising edges of at least some of the tiers;

a source tier underlying the stack structure and comprising;

a source structure; and

first discrete conductive structures horizontally separated from one another and the source structure by at least one dielectric material;

conductive contact structures on the steps of the staircase structure; and

first conductive pillar structures horizontally alternating with the conductive contact structures and vertically extending through the stack structure to the first discrete conductive structures of the source tier.

2. The microelectronic device of claim 1, wherein the source structure is electronically isolated from each of the first discrete conductive structures.

3. The microelectronic device of claim 1, wherein the source structure and the first discrete conductive structures have substantially the same material composition and vertical position as one another.

4. The microelectronic device of claim 1, further comprising:

second discrete conductive structures within the source tier and horizontally separated from one another, the first discrete conductive structures, and the source structure by the at least one dielectric material; and

second conductive pillar structures outside of horizontal boundaries of the staircase structure and vertically extending through the stack structure to the source structure and second discrete conductive structures.

5. The microelectronic device of claim 4, wherein the first conductive pillar structures and the second conductive pillar structures have substantially the same material composition and vertical dimensions as one another.

6. The microelectronic device of claim 4, wherein the source structure and the second discrete conductive structures are electrically connected to additional conductive structures underlying the source tier.

7. The microelectronic device of claim 6, wherein the first discrete conductive structures are electrically isolated from the additional conductive structures.

8. The microelectronic device of claim 1, wherein the first conductive pillar structures each individually physically contact one of the first discrete conductive structures.

9. The microelectronic device of claim 1, wherein the first conductive pillar structures are substantially horizontally aligned with the conductive contact structures.

10. The microelectronic device of claim 1, wherein the conductive structures of the stack structure comprise tungsten.

11. A memory device, comprising:

a stack structure comprising tiers each comprising at least one conductive structure and at least one insulating structure vertically adjacent the at least one conductive structure;

a staircase structure having steps comprising horizontal ends of at least some the tiers;

conductive contact structures in physical contact with the steps of the staircase structure;

discrete conductive structures underlying the stack structure;

conductive pillar structures horizontally interposed between and aligned with the conductive contact structures and vertically extending through the stack structure to the discrete conductive structures;

a source plate electrically isolated from and at substantially the same vertical position as the discrete conductive structures;

data lines overlying the stack structure;

strings of memory cells vertically extending through the stack structure and electrically coupled to the source plate and the data lines;

additional conductive lines electrically coupled to the conductive contact structures; and

a control device electrically coupled to the source plate, the data lines, and the additional conductive lines.

12. The memory device of claim 11, wherein the discrete conductive structures are each electrically isolated from all other conductive structures underlying the stack structure.

13. The memory device of claim 11, wherein one or more of the discrete conductive structures are electrically connected to one or more additional conductive structures thereunder.

14. The memory device of claim 11, further comprising additional discrete conductive structures horizontally interposed between and at substantially the same vertical position as the source plate and the discrete conductive structures.

15. The memory device of claim 14, wherein one or more of the additional discrete conductive structures are electrically connected to one or more additional conductive structures thereunder.

16. The memory device of claim 15, further comprising additional conductive pillar structures vertically extending through the stack structure to the additional discrete conductive structures.

17. The memory device of claim 11, wherein the control device comprises CMOS circuitry and is at least partially positioned vertically below and within horizontal boundaries of a region of the stack structure containing the strings of memory cells.

18. A 3D NAND Flash memory device, comprising:

a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising at least one of the conductive structures and at least one of the insulating structures;

a staircase structure having steps comprising edges of at least some of the tiers of the stack structure;

a source tier underlying the stack structure and comprising;

a source plate; and

discrete conductive structures horizontally separated from one another and the source plate by a dielectric material;

contact structures on the steps of the staircase structure;

support structures horizontally between the contact structures and vertically extending through the stack structure to the discrete conductive structures of the source tier;

data lines overlying the stack structure;

an array of vertically-extending strings of memory cells extending through the stack structure and electrically connected to the source plate, and the data lines;

conductive lines electrically connected to the contact structures; and

a control device vertically underlying the source tier and within horizontal boundaries of the array of vertically-extending strings of memory cells, the control device electrically coupled to the source plate, the data lines, and the conductive lines.

19. The 3D NAND Flash memory device of claim 18, wherein the control device comprises CMOS circuitry.

20. The 3D NAND Flash memory device of claim 18, wherein the discrete conductive structures and the source plate of the source tier are electrically isolated from one another.

21. The 3D NAND Flash memory device of claim 18, wherein the support structures each individually comprise:

an electrically conductive pillar structure; and

a dielectric liner material substantially covering sidewalls of the electrically conductive pillar structure.

22. The 3D NAND Flash memory device of claim 18, wherein the source tier further comprises additional discrete conductive structures horizontally separated from one another, the discrete conductive structures, and the source plate by the dielectric material.

23. The 3D NAND Flash memory device of claim 18, wherein the support structures horizontally alternate with the contact structures and are substantially horizontally aligned with the contact structures.

24. An electronic system, comprising:

an input device;

an output device;

a processor device operably coupled to the input device and the output device; and

a memory device operably coupled to the processor device and comprising at least one microelectronic device structure comprising;

a stack structure comprising tiers each comprising an electrically conductive structure and a dielectric structure vertically neighboring the electrically conductive structure;

a staircase structure within the stack structure and exhibiting steps comprising edges of at least some of the tiers;

a source tier vertically below the stack structure and comprising;

a source structure;

first discrete conductive structures electrically isolated from one another and the source structure; and

second discrete conductive structures horizontally separated from one another, the source structure, and the first discrete conductive structures;

conductive contact structures on the steps of the staircase structure;

first conductive pillar structures vertically extending through the stack structure at the staircase structure to the first discrete conductive structures of the source tier; and

second conductive pillar structures vertically extending through the stack structure to the second discrete conductive structures of the source tier.

25. The electronic system of claim 24, wherein the memory device comprises a multi-deck 3D NAND Flash memory device.