Semiconductor device and method for manufacturing the same

• US 10,580,877 B2
• Filed: 03/21/2019
• Issued: 03/03/2020
• Est. Priority Date: 02/19/2013
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki
• Primary Examiner(s): Landau, Matthew C
• Assistant Examiner(s): Yemelyanov, Dmitriy
• Application Number:
  US16/360,775
• Publication Number:
  US 20190221651A1
• Time in Patent Office: 348 Days
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66045 Field-effect transistors
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first conductivity type formed with a first trench;

a gate electrode buried in the first trench via an insulating film;

a source region of the first conductivity type disposed in a manner exposed on a surface of the semiconductor layer and contacting a first part of a side face of the first trench;

a channel region of a second conductivity type disposed on the source region on a back surface side relative to the semiconductor layer, in a manner contacting the source region and a second part of the side face of the first trench;

a drain region of the first conductivity type disposed on the channel region on the back surface side relative to the semiconductor layer, in a manner contacting the channel region and a bottom face of the first trench;

an active region that forms a channel in the channel region to perform a transistor operation;

an outer peripheral region disposed around the active region, and

a surface insulating film disposed above the semiconductor layer, and the surface insulating film has a first portion that is disposed in the active region and a second portion that is disposed in the outer peripheral region, and the first portion of the surface insulating film is thinner than the second portion of the surface insulating film,

wherein in the surface insulating film, a contact hole that selectively exposes the source region is formed substantially over the entire surface of the semiconductor layer.

2. The semiconductor device according to claim 1, further comprising:

a channel contact region of a second conductivity type selectively disposed on a surface side relative to the semiconductor layer, such that the channel contact region is electrically connected with the channel region; and

a surface metal layer electrically connected with the source region and the channel contact region.

3. The semiconductor device according to claim 2, further comprising a second conductivity-type layer formed in a manner contacting the channel region and the channel contact region.

4. The semiconductor device according to claim 1, wherein the gate electrode is a metal gate electrode containing polysilicon.

5. The semiconductor device according to claim 2, wherein the surface metal layer is made of a metal containing titanium (Ti).

6. The semiconductor device according to claim 5, wherein the surface metal layer includes a laminated structure (Ti/TiN) of titanium (Ti) and titanium nitride (TiN).

7. The semiconductor device according to claim 1, wherein the first portion of the surface insulating film has a thickness of approximately 5000 Å

or less in the active region.

8. The semiconductor device according to claim 1, wherein in the semiconductor layer, a unit cell that forms a channel in the channel region to perform a transistor operation are defined in a grid shape by the first trench.

9. The semiconductor device according to claim 1, wherein in the semiconductor layer, a unit cell that forms a channel in the channel region to perform a transistor operation are defined in a striped shape by the first trench.

10. The semiconductor device according to claim 1, wherein the semiconductor layer is made of SiC, GaN, or diamond.