Oxygen inserted Si-layers for reduced contact implant outdiffusion in vertical power devices

• US 10,580,888 B1
• Filed: 08/08/2018
• Issued: 03/03/2020
• Est. Priority Date: 08/08/2018
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Blank, Oliver, Feil, Thomas, Roesch, Maximilian, Poelzl, Martin, Haase, Robert, Leomant, Sylvain, Goller, Bernhard, Meiser, Andreas
• Primary Examiner(s): Harrison, Monica D
• Application Number:
  US16/058,631
• Publication Number:
  US 20200052109A1
• Time in Patent Office: 573 Days
• Field of Search: 257330
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/3063 Electrolytic etching
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 29/0856 Source regions
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and a portion of the body region, the contact trench being filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure formed along the sidewall of the contact trench and disposed between the highly doped body contact region and the channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si.

Claims

1. A semiconductor device, comprising:

a gate trench extending into a Si substrate;

a body region in the Si substrate, the body region including a channel region which extends along a sidewall of the gate trench;

a source region in the Si substrate above the body region;

a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and a portion of the body region, the contact trench being filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench; and

a diffusion barrier structure formed along the sidewall of the contact trench and disposed between the highly doped body contact region and the channel region, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si.

2. The semiconductor device of claim 1, wherein the diffusion barrier structure extends along the bottom of the contact trench.

3. The semiconductor device of claim 1, wherein the highly doped body contact region is only laterally confined by the diffusion barrier structure which is absent from the bottom of the contact trench.

4. The semiconductor device of claim 1, wherein the electrically conductive material which fills the contact trench extends onto a front main surface of the Si substrate beyond the diffusion barrier structure and in a direction toward the gate trench.

5. The semiconductor device of claim 1, wherein the diffusion barrier structure comprises a capping layer of Si epitaxially grown on the alternating layers of Si and oxygen-doped Si.

6. A method of manufacturing a semiconductor device, the method comprising:

forming a gate trench which extends into a Si substrate;

forming a contact trench which extends into the Si substrate and is separate from the gate trench;

forming a highly doped body contact region in the Si substrate at a bottom of the contact trench;

forming a diffusion barrier structure along a sidewall of the contact trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si;

forming a body region in the Si substrate, the body region including a channel region which extends along a sidewall of the gate trench;

forming a source region in the Si substrate above the body region; and

filling the contact trench with an electrically conductive material which contacts the source region at the sidewall of the contact trench and the highly doped body contact region at the bottom of the contact trench.

7. The method of claim 6, wherein forming the diffusion barrier structure comprises:

before filling the contact trench with the electrically conductive material, epitaxially growing the alternating layers of Si and oxygen-doped Si on the sidewall and the bottom of the contact trench.

8. The method of claim 7, further comprising:

epitaxially growing a capping layer of Si on the alternating layers of Si and oxygen-doped Si.

9. The method of claim 7, wherein forming the highly doped body contact region comprises:

implanting a dopant species into the alternating layers of Si and oxygen-doped Si at the bottom of the contact trench; and

annealing the Si substrate to activate the implanted dopant species.

10. The method of claim 7, further comprising:

removing the alternating layers of Si and oxygen-doped Si from at least part of the bottom of the contact trench.

11. The method of claim 10, wherein removing the alternating layers of Si and oxygen-doped Si from at least part of the bottom of the contact trench comprises:

epitaxially growing a capping layer of Si on the alternating layers of Si and oxygen-doped Si;

depositing a conformal spacer oxide on the capping layer of Si;

anisotropically etching the conformal spacer oxide to expose the diffusion barrier structure at the bottom of the contact trench;

etching away the exposed diffusion barrier structure at the bottom of the contact trench; and

after etching away the exposed diffusion barrier structure at the bottom of the contact trench, removing the conformal spacer oxide.

12. The method of claim 6, wherein forming the diffusion barrier structure comprises:

before filling the contact trench with the electrically conductive material, epitaxially growing the alternating layers of Si and oxygen-doped Si only on the sidewall and not the bottom of the contact trench.

13. The method of claim 12, further comprising:

epitaxially growing a capping layer of Si on the alternating layers of Si and oxygen-doped Si.

14. The method of claim 12, wherein forming the highly doped body contact region comprises:

implanting a dopant species into the bottom of the contact trench which is devoid of the alternating layers of Si and oxygen-doped Si; and

annealing the Si substrate to activate the implanted dopant species.

15. The method of claim 6, further comprising:

before filling the contact trench with the electrically conductive material, etching back an insulating layer formed on a front main surface of the Si substrate so that the insulating layer has an opening which is aligned with the contact trench and wider than a combined width of the contact trench and the diffusion barrier structure.

16. The method of claim 15, wherein filling the contact trench with the electrically conductive material comprises:

depositing the electrically conductive material in the contact trench and in the opening formed in the insulating layer, so that the electrically conductive material extends onto the front main surface of the Si substrate beyond the diffusion barrier structure and in a direction toward the gate trench.

17. The method of claim 6, wherein forming the diffusion barrier structure comprises:

before forming the body and the source regions, epitaxially growing the alternating layers of Si and oxygen-doped Si on the sidewall and the bottom of the contact trench.

18. The method of claim 17, further comprising:

before forming the body and the source regions, epitaxially growing a capping layer of Si on the alternating layers of Si and oxygen-doped Si.

19. The method of claim 17, further comprising:

removing the alternating layers of Si and oxygen-doped Si from at least part of the bottom of the contact trench.

20. The method of claim 19, wherein removing the alternating layers of Si and oxygen-doped Si from at least part of the bottom of the contact trench comprises:

epitaxially growing a capping layer of Si on the alternating layers of Si and oxygen-doped Si;

depositing a conformal spacer oxide on the capping layer of Si;

anisotropically etching the conformal spacer oxide to expose the diffusion barrier structure at the bottom of the contact trench;

etching away the exposed diffusion barrier structure at the bottom of the contact trench; and

after etching away the exposed diffusion barrier structure at the bottom of the contact trench, removing the conformal spacer oxide.

21. The method of claim 6, wherein forming the diffusion barrier structure comprises:

before forming the body and the source regions, forming a sacrificial insulating layer at the bottom of the contact trench;

after forming the sacrificial insulating layer, epitaxially growing the alternating layers of Si and oxygen-doped Si on the sidewall of the contact trench; and

after epitaxially growing the alternating layers of Si and oxygen-doped Si, removing the sacrificial insulating layer from the bottom of the contact trench.

22. The method of claim 6, further comprising:

after forming the diffusion barrier structure and before forming the source and the body regions, filling the contact trench with a sacrificial plug material;

after filling the contact trench with the sacrificial plug material, forming the source and the body regions in the Si substrate;

after forming the source and the body regions, removing the sacrificial plug material;

after removing the sacrificial plug material and before filling the contact trench with the electrically conductive material, implanting a dopant species into the bottom of the contact trench; and

annealing the Si substrate to activate the implanted dopant species to form the highly doped body contact region.