Semiconductor device and method for fabricating the same

• US 10,580,891 B2
• Filed: 11/16/2018
• Issued: 03/03/2020
• Est. Priority Date: 10/14/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sung-Soo, Park, Gi-Gwan, Kang, Sang-Koo, Ryu, Koung-Min, Lee, Jae-Hoon, Ha, Tae-Won
• Primary Examiner(s): Han, Jonathan
• Application Number:
  US16/193,521
• Publication Number:
  US 20190088779A1
• Time in Patent Office: 473 Days
• Field of Search: 257E21444, 257E29255, 257407, 438183, 438216, 438197
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

Claims

1. A semiconductor device, comprising:

a substrate including a first region and a second region;

a first gate spacer on the first region, the first gate spacer defining a first trench;

a second gate spacer on the second region, the second gate spacer defining a second trench;

a first gate electrode filling the first trench;

a second gate electrode filling the second trench;

a first interlayer insulating layer on the substrate, the first interlayer insulating layer surrounding the first gate spacer; and

a second interlayer insulating layer on the substrate, the second interlayer insulating layer surrounding the second gate spacer,

wherein the first interlayer insulating layer and the second interlayer insulating layer each includes a lower portion and an upper portion,

the upper portion of the first interlayer insulating layer and the upper portion of the second interlayer insulating layer each include germanium, and

the lower portion of the first interlayer insulating layer and the lower portion of the second interlayer insulating layer each do not include germanium.

2. The semiconductor device of claim 1, wherein with increasing distance from the substrate, a width of the first trench is substantially same, and a width of the second trench increases.

3. The semiconductor device of claim 1, wherein with increasing distance from the substrate, a width of the first trench decreases, and a width of the second trench increases.

4. The semiconductor device of claim 1, wherein a thickness of the upper portion of the first interlayer insulating layer is less than a thickness of the upper portion of the second interlayer insulating layer.

5. The semiconductor device of claim 4, wherein with increasing distance from the substrate, a width of the first trench is substantially same, and a width of the second trench decreases.

6. The semiconductor device of claim 1, wherein an amount of the germanium included in the upper portion of the first interlayer insulating layer is less than an amount of the germanium included in the upper portion of the second interlayer insulating layer.

7. The semiconductor device of claim 6, wherein with increasing distance from the substrate, a width of the first trench is substantially same, and a width of the second trench decreases.

8. The semiconductor device of claim 1, further comprising:

a first fin-type pattern and a second fm-type pattern both protruding from the substrate,

wherein the first gate electrode intersects with the first fin-type pattern, and the second gate electrode intersects with the second fin-type pattern.

9. A semiconductor device, comprising:

a substrate including a first region and a second region;

a first gate spacer on the first region, the first gate spacer defining a first trench, a sidewall of the first trench having a slope of a first sign with respect to a bottom surface of the first trench;

a second gate spacer on the second region, the second gate spacer defining a second trench, a sidewall of the second trench having a slope of a second sign with respect to a bottom surface of the second trench, the second sign being opposite to the first sign;

a first gate electrode filling the first trench;

a second gate electrode filling the second trench; and

an interlayer insulating layer on the substrate, the interlayer insulating layer surrounding the first gate spacer and the second gate spacer, the interlayer insulating layer including a first portion having an element semiconductor material,

wherein a thickness of the first portion of the interlayer insulating layer in the first region is different from a thickness of the first portion of the interlayer insulating layer in the second region.

10. The semiconductor device of claim 9, wherein the element semiconductor material comprises at least one of germanium (Ge) or silicon (Si).

11. The semiconductor device of claim 9, wherein the interlayer insulating layer include a second portion which does not include the element semiconductor material.

12. The semiconductor device of claim 9, wherein an amount of the element semiconductor material included in the first portion of the interlayer insulating layer in the first region is different from an amount of the element semiconductor material included in the first portion of the interlayer insulating layer in the second region.

13. The semiconductor device of claim 9, further comprising:

a third gate electrode on the first region, the third gate electrode being adjacent to the first gate electrode; and

a fourth gate electrode on the second region, the fourth gate electrode being adjacent to the second gate electrode,

wherein a spacing between a bottom surface of the first gate electrode and a bottom surface of the third gate electrode is different from a spacing between a bottom surface of the second gate electrode and a bottom surface of the fourth gate electrode.

14. The semiconductor device of claim 13, wherein a thickness of the first portion of the interlayer insulating layer in the first region is substantially same as a thickness of the first portion of the interlayer insulating layer in the second region.