Detecting single event upsets and stuck-at faults in RAM-based data path controllers

• US 10,585,747 B2
• Filed: 08/22/2018
• Issued: 03/10/2020
• Est. Priority Date: 05/16/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pierce, David A.
• Primary Examiner(s): Vallecillo, Kyle
• Application Number:
  US16/109,621
• Publication Number:
  US 20180365100A1
• Time in Patent Office: 566 Days
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 2211/104 Metadata, i.e. metadata associated with RAID systems with parity
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

In one embodiment, a system includes logic configured to receive data comprising a plurality of data elements, where each data element comprises one or more bits. Further, the logic is configured to output bursts of data comprising the plurality of data elements along with a number of parity bits equal to a number of data elements in the plurality of data elements received from a first parity module to an input of a data path. Further still, the system includes a binary sequence generator configured to create a binary sequence comprising a plurality of bonus bits in a pseudo-random pattern that has less than a predetermined chance of matching any sequence of bits in the data while in the data path. Further still, the first parity module is configured to provide a parity calculation prior to passing the plurality of data elements to the input of the data path.

Claims

1. A system, comprising:

a hardware processor; and

logic integrated with the hardware processor, executable by the hardware processor, or integrated with and executable by the hardware processor, the logic being configured to;

receive data comprising a plurality of data elements, each data element comprising one or more bits; and

output bursts of data comprising the plurality of data elements along with a number of parity bits equal to a number of data elements in the plurality of data elements received from a first parity module to an input of a data path, each parity bit corresponding to a single data element, wherein each burst of data is restricted from being greater in length than a predetermined maximum burst size;

a first binary sequence generator comprising at least one linear feedback shift register (LFSR) implemented in hardware, the first binary sequence generator being configured to create a binary sequence comprising a plurality of bonus bits in a pseudo-random pattern that has less than a predetermined chance of matching any sequence of bits in the data while in the data path, wherein a total length of the binary sequence is equal to or greater than the predetermined maximum burst size; and

the first parity module configured to provide a parity calculation prior to passing the plurality of data elements to the input of the data path, the parity calculation using bits of each data element along with a bonus bit from the binary sequence to produce a corresponding parity bit for each data element.

2. The system as recited in claim 1, wherein the logic is further configured to:

receive the bursts of data comprising each data element along with its corresponding parity bit at an output of the data path; and

analyze a result to determine whether an error has occurred to the data in the data path,

wherein the system further comprises;

a second binary sequence generator configured to create the binary sequence at the output of the data path; and

a second parity module configured to produce the result based on bits of each data element from the bursts of data along with its corresponding parity bit received at the output of the data path and a bonus bit from the binary sequence generated by the second binary sequence generator.

3. The system as recited in claim 2, wherein the second binary sequence generator is matched to the first binary sequence generator.

4. The system as recited in claim 2, wherein the bursts of data received at the output of the data path have burst sizes that are equal to a burst size of the bursts of data that entered the input of the data path.

5. The system as recited in claim 2, wherein the logic configured to analyze the result is further configured to determine whether the result is zero, wherein a zero result indicates that no error occurred to the data while in the data path, and wherein a non-zero indicates that an error occurred to the data while in the data path.

6. The system as recited in claim 2, wherein the first binary sequence generator comprises one or more linear feedback shift registers (LFSRs), and wherein the binary sequence is a pseudo-random binary sequence.

7. The system as recited in claim 2, wherein the second binary sequence generator comprises one or more linear feedback shift registers (LFSRs), and wherein the binary sequence is a pseudo-random binary sequence.

8. The system as recited in claim 1, wherein the data path comprises at least one element selected from a group of elements comprising:

a first-in-first-out (FIFO) buffer, a store and forward buffer, a random access memory (RAM), sequential logic, and a flash memory.

9. The system as recited in claim 1, wherein meta data is included in the parity calculation to produce the parity bit.

10. A method, comprising:

receiving, by a processing circuit, data comprising a plurality of data elements, each data element comprising one or more bits;

using a first binary sequence generator comprising at least one linear feedback shift register (LFSR) implemented in hardware to create a binary sequence comprising a plurality of bonus bits in a pseudo-random pattern that has less than a predetermined chance of matching any sequence of bits in the data while in a data path, wherein a total length of the binary sequence is equal to or greater than a predetermined maximum burst size;

using a first parity module to provide a parity calculation prior to passing the plurality of data elements to an input of the data path, the parity calculation using bits of each data element along with a bonus bit from the binary sequence to produce a corresponding parity bit for each data element; and

outputting, by the processing circuit, bursts of data comprising the plurality of data elements along with a number of parity bits equal to a number of data elements in the plurality of data elements received from a first parity module to the input of the data path, each parity bit corresponding to a single data element, wherein each burst of data is restricted from being greater in length than the predetermined maximum burst size.

11. The method of claim 10, further comprising:

receiving the bursts of data comprising each data element along with its corresponding parity bit at an output of the data path;

creating the binary sequence at the output of the data path using a second binary sequence generator;

using a second parity module to produce a result based on bits of each data element from the bursts of data along with its corresponding parity bit received at the output of the data path and a bonus bit from the binary sequence generated by the second binary sequence generator; and

analyzing the result to determine whether an error has occurred to the data in the data path.

12. The method of claim 11, wherein the second binary sequence generator is matched to the first binary sequence generator, and wherein the bursts of data received at the output of the data path have burst sizes that are equal to a burst size of the bursts of data that entered the input of the data path.

13. The method of claim 11, wherein the analyzing the result comprises determining whether the result is zero, wherein a zero result indicates that no error occurred to the data while in the data path, and wherein a non-zero indicates that an error occurred to the data while in the data path.

14. The method of claim 11, wherein the first binary sequence generator and the second binary sequence generator each comprise one or more linear feedback shift registers (LFSRs), and wherein the binary sequence is a pseudo-random binary sequence.

15. The method of claim 10, wherein the data path comprises at least one element selected from a group of elements comprising:

a first-in-first-out (FIFO) buffer, a store and forward buffer, a random access memory (RAM), sequential logic, and a flash memory.

16. The method of claim 10, wherein meta data is included in the parity calculation to produce the parity bit.

17. A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the embodied program instructions executable by a processor to cause the processor to:

receive, by the processor, data comprising a plurality of data elements, each data element comprising one or more bits;

use, by the processor, a first binary sequence generator comprising at least one linear feedback shift register (LFSR) implemented in hardware to create a binary sequence comprising a plurality of bonus bits in a pseudo-random pattern that has less than a predetermined chance of matching any sequence of bits in the data while in a data path, wherein a total length of the binary sequence is equal to or greater than a predetermined maximum burst size;

use, by the processor, a first parity module to provide a parity calculation prior to passing the plurality of data elements to an input of the data path, the parity calculation using bits of each data element along with a bonus bit from the binary sequence to produce a corresponding parity bit for each data element; and

output, by the processor, bursts of data comprising the plurality of data elements along with a number of parity bits equal to a number of data elements in the plurality of data elements received from a first parity module to the input of the data path, each parity bit corresponding to a single data element, wherein each burst of data is restricted from being greater in length than the predetermined maximum burst size.

18. The computer program product of claim 17, wherein the embodied program instructions are further executable by the processor to cause the processor to:

receive, by the processor, the bursts of data comprising each data element along with its corresponding parity bit at an output of the data path;

create, by the processor, the binary sequence using a second binary sequence generator at the output of the data path;

use, by the processor, a second parity module configured to produce a result based on bits of each data element from the bursts of data along with its corresponding parity bit received at the output of the data path and a bonus bit from the binary sequence generated by the second binary sequence generator; and

analyze, by the processor, the result to determine whether an error has occurred to the data in the data path.

19. The computer program product of claim 18, wherein the second binary sequence generator is matched to the first binary sequence generator, and wherein the bursts of data received at the output of the data path have burst sizes that are equal to a burst size of the bursts of data that entered the input of the data path.

20. The computer program product of claim 19, wherein the embodied program instructions executable to analyze the result further cause the processor to determine whether the result is zero, wherein a zero result indicates that no error occurred to the data while in the data path, and wherein a non-zero indicates that an error occurred to the data while in the data path.