Semiconductor process modeling to enable skip via in place and route flow
First Claim
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1. A method for incorporating skip vias in a place and route flow of an integrated circuit design, the method comprising:
- employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer;
automatically adding the skip vias during the place and route flow; and
when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via in a newly generated physical layout.
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Abstract
A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.
18 Citations
5 Claims
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1. A method for incorporating skip vias in a place and route flow of an integrated circuit design, the method comprising:
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employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer;
automatically adding the skip vias during the place and route flow; andwhen a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via in a newly generated physical layout. - View Dependent Claims (2, 3, 4, 5)
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Specification
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsShao, Dongbing, Xu, Zheng, Clevenger, Lawrence A.
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Primary Examiner(s)Ngo, Brian
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Application NumberUS15/962,461Publication NumberTime in Patent Office685 DaysField of Search716110, 716111, 716118, 716119, 716126US Class CurrentCPC Class CodesG06F 2111/04 Constraint-based CADG06F 2111/20 Configuration CAD, e.g. des...G06F 30/392 Floor-planning or layout, e...G06F 30/394 Routing G06F30/396 takes pr...G06F 30/398 Design verification or opti...
